postdoc position in Spain related to semiconductor device modeling

As Professor in the Universitat Rovira i Virgili (Tarragona, Catalonia, , Spain), I am going to apply for a postdoctoral position (funded by the Spanish Ministry) related to modeling (in particular compact modeling) and/or parameter extraction of emerging devices we are targeting, such as Multi-Gate MOSFETs, junctionless nanowires, III-V MOSFETs, GaN HEMTs, Tunnel FETs, and also organic and metal oxide TFTs.

The candidate should be a person who holds a PhD as awarded after September 1 2009, or who is committed to defend his Ph D thesis in the coming months (before the start of the contract).

Contracts are expected to start after September 2014.
The candidate should have enough research experience in the field of semiconductor devices, and must have a very good knowledge of the physics of electron devices. The research project to be carried out can be adapted to the candidate's profile.

The work may continue the work we did in the framework of some EU-funded projects, such as COMON (about Multi-Gate MOSFETs, GaN HEMTs, and High Voltage MOSFETs), SQWIRE (junctionless Si nanowires) and FlexNET (organic TFTs) . Our contribution in these projects was the physics and modeling (in particular compact modeling) of the novel devices addressed by these European projects.

The postdoc position, which will be a contract, will have a duration of up to 2 years. The net salary will be around 1900 Euro/months.

Interested applicants should send me their CV by e-mail.
DEADLINE TO RECEIVE APPLICATIONS: February 24 2014

MY E-MAIL ADDRESS IS: benjamin.iniguez@urv.cat

Address:
Benjamin Iñiguez
Nanoelectronics and Photonics Systrems Group (NEPHOS)
Department of Electronic Engineering
Universitat Rovira i Virgili (URV)
Avinguda dels Paisos Catalans 26
43007 Tarragona, Catalonia
SPAIN.

Standards For FinFETs

   http://electronicdesign.com/eda/synopsys-rich-goldman-explains-effects-standards-2014s-semiconductor-trends 

Rich Goldman, VP of corporate marketing and strategic alliances at Synopsys, recently predicted the top five trends that are likely to drive the global semiconductor industry in 2014. Standards will help, or hurt, each of these trends.

The ever-changing semiconductor industry has experienced and will continue to experience megatrends like no other industry. Recently, Rich Goldman, vice president of corporate marketing and strategic alliances at Synopsys, made his predictions about the top five trends that are likely to drive the global semiconductor industry in 2014. Each of these trends can be helped, or hurt, by the domain of standards.

Standards For FinFETs

Karen: You predict that FinFETs will be one of the top five trends in 2014. FinFETs promise lower power consumption and higher performance. Designing and manufacturing FinFETs involve a slew of challenges. How can standards help overcome some of them?

Rich: EDA tools and models are advancing to handle the unique properties and behaviors of FinFETs. For each step in the design cycle, data is transferred from one tool to another. Enabling interoperability and modeling are obvious roles for standards to play and there are already several standards in use today. For example, the Liberty library modeling standard is used to develop FinFET libraries that feed logic synthesis and other advanced tools. Standards for describing low-power design intent are also important. Because low power consumption is a key feature of FinFETs, designers can benefit from using these during the power planning stage. The Unified Power Format (UPF) (IEEE Std. 1801) is effective in capturing the low-power design intent and directing the EDA tools to implement it. The biggest advancements in standards for FinFETs are in the Interconnect Technology Format (ITF) standardized by the IEEE-ISTO and in the new BSIM-CMG (CMOS Multi-Gate) SPICE model.

Karen: Are these standards sufficient for FinFETs today?

Rich: Standards for advanced semiconductor design, including FinFETs, should always evolve. While the standards may suffice for a given technology or geometry node, design and EDA engineers are constantly inventing more effective ways of overcoming challenges. As these engineers learn new techniques, the standards for interoperability and modeling need to be enhanced. It’s a cyclical situation. The standards enable new designs that can render the standards obsolete unless the standards are updated to include new methods and technology. Thus, standards working groups, comprised of tech-savvy engineers and experts in standards development, are part of the overall success of new technologies such as FinFETs.

[continue reading...]

New i-MOS Release

http://i-mos.org/
A new release of the interactive Modeling and On-line Simulation Platform (i-MOS), version 201401 is available online. In this release, the i-MOS team launched several new services, as well as improved some modules in previous versions. A list of these new features follows:

• Evaluative support for BSIM3 with newly designed interfaces;
• A collection of model parameter cards for your applications;
• A newly implemented double-gate/FinFET model SDDGM; 
• Parameter searching function for all the device models;
• Integrated text editor for composing netlists in circuit simulations;
• Easier entry for your posting of news and events, etc.

For more details and an updated user manual, please see http://i-mos.org

Other related compact/SPICE modeling events and news are listed at:
http://i-mos.org/imos/resources

[Call for Papers] SISPAD2014

https://sites.google.com/site/sispad2014/

This is a call for papers for the 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD2014), to be held September 9-11, 2014, in Yokohama, Japan. This conference provides an opportunity for the presentation and discussion of the latest advances in modeling and simulation of semiconductor devices, processes, and equipment for integrated circuits.

Abstract submission deadline is March 31, 2014.

Workshops:
Two companion workshops will run concurrently prior to the start of the conference on Monday 8th September 2014:

• Workshop 1: Compact Modeling -Enabling Better Insight of Device Features-
  Organizer: Mitiko Miura-Mattausch (Hiroshima University)
• Workshop 2: Carrier Transport in Nano-MOS Transistors: Theory and Experiments(tentative)
  Organizer: Hideaki Tsuchiya (Kobe University) and Yoshinari Kamakura (Osaka University)

Plenary Speakers:

• Augusto Benvenuti (Micron Technology)
  Current status and future prospects of non-volatile memory modeling
• Massimo V. Fischetti (University of Texas at Dallas)
  Physics of electronic transport in low-dimensionality materials forfuture FETs
• Kimimori Hamada (Toyota Motor Corporation)
  TCAD challenge on development of power semiconductor devices for automotive applications

Invited Speakers:

• Mario Ancona (Naval Research Laboratory)
  Nonlinear thermoelectroelastic simulation of III-N devices
• Asen Asenov (University of Glasgow)
  Progress in the simulation of time dependent statistical variability in nano CMOS transistors
• Jean-Pierre Colinge (Taiwan Semiconductor Manufacturing Company)
  Nanowire transistors: pushing Moore's law to the limit
• Tibor Grasser (Vienna University of Technology)
  Advanced modeling of charge trapping: RTN, 1/f noise, SILC, and BTI
• Kohji Mitsubayashi (Tokyo Medical and Dental University)
  Novel biosensing devices for medical applications
• Christian Sandow (Infineon Technologies)
  Exploring the limits of the safe operation area of power semiconductor devices
• Mark Stettler (Intel Corporation)
  Device and process modeling: 20 years at Intel's other fab

Call for IJNM papers: Noise modeling of high-frequency semiconductor devices

INTERNATIONAL JOURNAL OF NUMERICAL MODELLING: ELECTRONIC NETWORKS, DEVICES AND FIELDS Int. J. Numer. Model. (2014)

Call for IJNM papers: Noise modeling of high-frequency semiconductor devices 

Noise processes in solid-state active devices often determine their fundamental operational limits. This is especially true in situations where a device operates under tight sensitivity and accuracy constraints, as is the case in satellite communication systems, aerospace instrumentation, and deep-space radio astronomy. Today’s ultra-high frequency transistors that meet these demanding low-noise performance characteristics often leverage progressive device downscaling techniques in conjunction with improved semiconductor alloys. 

To enable the design of next-generation low-noise devices, however, accurate and flexible models that characterize the connection between the physics of microscopic noise processes and measurable macroscopic performance are called for. The objective of this Special Issue is to collect and disseminate recent results addressing the topic of modeling and simulation of the macroscopic noise performance of high- frequency transistors including but not limited to GaAs-based and GaN-based field-effect transistors, Si metal–oxide–semiconductor FETs and FinFETs, InP-based high-electron-mobility transistors, and GaAs and SiGe heterojunction bipolar transistors. It is worth pointing out that because of frequency up-conversion phenomena caused by a device’s nonlinearities, low frequency noise processes may strongly impact microwave and millimeter wave behavior as well. Contributions focusing on low-frequency noise modeling therefore will be considered as well. 

This issue will include both invited and contributed manuscripts.

Manuscripts for this Special Issue should adhere to the requirements for regular papers of the IJNM as specified in the Author Guidelines at 

http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1099-1204/ homepage/ForAuthors.html. 

Potential contributors may contact the Guest Editors to determine the suitability of their contribution to the Special Issue. All manuscripts should be submitted via the IJNM’s manuscript website, with a statement that they are intended for this Special Issue. 

Guest Editors: 
Prof. Alina Caddemi University of Messina, Italy Email:
Prof. Ernesto Limiti University of Rome Tor Vergata, Italy Email:

Manuscript submission deadline: July 31, 2014