Showing posts with label openLANE. Show all posts
Showing posts with label openLANE. Show all posts

Mar 25, 2026

[Open Source Survey] From RTL to Fabrication

Emilio Isaac Baungarten-Leon
From RTL to Fabrication: Survey of Open-Source EDA Tools and PDKs
Electronics 2026, 15(5), 1048;
DOI: 10.3390/electronics15051048

* Departamento de Electromecánica, Universidad Autónoma de Guadalajara, Zapopan 45129, Mexico


Abstract: This article aims to synthesize the current ecosystem of open-source tools for Integrated Circuit (IC) design, covering the entire digital design flow from Register-Transfer Level (RTL) description to fabricable layouts. The survey categorizes and analyzes tools across major stages of design, including code-generation tools, logic synthesis, simulation, and physical design flow. Special emphasis is given to the fabricable open-source Process Design Kit (PDK), which enables the physical realization of open-hardware projects. By examining interoperability, limitations, and maturity across this toolchain, the article provides a comprehensive overview of the Electronic Design Automation (EDA) landscape and identifies the research and educational opportunities that arise from democratizing silicon design through open and reproducible workflows.
Fig: (a) IC design flow illustrating the complete process from RTL specification through logic synthesis, physical design (floorplanning, placement, clock tree synthesis, routing), verification, and final GDSII generation for fabrication. (b) FPGA design flow showing the progression from RTL description to synthesis, technology mapping, placement-and-routing on the target FPGA fabric, bitstream generation, and device configuration.

Acknowledgments: The APC was funded by Universidad Autónoma de Guadalajara (UAG), financial support provided through its Fondo Semilla. The author gratefully acknowledges the Universidad Autónoma de Guadalajara (UAG) for the financial support provided through its Fondo Semilla program, which covered the article processing charges and enabled the publication of this work. During the preparation of this manuscript, the authors utilized GPT-5.2 solely to enhance the clarity, grammar, and overall quality of the English text. The author reviewed and edited all AI-assisted content and takes full responsibility for the accuracy, originality, and integrity of the final manuscript.

Table A1. Main open-source EDA tools and their official repositories
Category Tool Official Link
Code-Generation ToolsPandA Bambu HLShttps://github.com/ferrandi/PandA-bambu (accessed on 20 January 2026)
Kiwi Compilerhttps://www.cl.cam.ac.uk/~djg11/kiwi/ (accessed on 20 January 2026)
LegUp HLShttps://github.com/LegUpComputing/legup-examples?tab=readme-ov-file (accessed on 20 January 2026)
ROCCChttp://roccc.cs.ucr.edu/ (accessed on 20 January 2026)
PyMTL3https://github.com/pymtl/pymtl3 (accessed on 20 January 2026)
Chiselhttps://www.chisel-lang.org/ (accessed on 20 January 2026)
SpinalHDLhttps://github.com/SpinalHDL/SpinalHDL (accessed on 20 January 2026)
Pyveriloghttps://github.com/PyHDI/Pyverilog (accessed on 20 January 2026)
Amaranth HDLhttps://github.com/amaranth-lang (accessed on 20 January 2026)
LLM-Based Code GenerationRTLCoderhttps://github.com/hkust-zhiyao/RTL-Coder (accessed on 20 January 2026)
Spec2RTL-Agenthttps://cirkitly.kernex.sbs/ (accessed on 20 January 2026)
OriGenhttps://github.com/pku-liang/OriGen (accessed on 20 January 2026)
AutoChiphttps://github.com/shailja-thakur/AutoChip (accessed on 20 January 2026)
CodeVhttps://github.com/cluesmith/codev (accessed on 20 January 2026)
VeriCoderhttps://github.com/Anjiang-Wei/VeriCoder (accessed on 20 January 2026)
StarCoderhttps://github.com/bigcode-project/starcoder (accessed on 20 January 2026)
CodeLlamahttps://github.com/meta-llama/codellama (accessed on 20 January 2026)
DeepSeek-Coderhttps://github.com/deepseek-ai/DeepSeek-Coder (accessed on 20 January 2026)
CodeQwenhttps://github.com/QwenLM/qwen-code (accessed on 20 January 2026)
Geminihttps://gemini.google.com/ (accessed on 20 January 2026)
GPThttps://chatgpt.com/ (accessed on 20 January 2026)
ChatEDAhttps://github.com/wuhy68/ChatEDA (accessed on 20 January 2026)
Synthesis ToolsYosyshttps://yosyshq.net/yosys/ (accessed on 20 January 2026)
ABC (Berkeley)https://people.eecs.berkeley.edu/~alanmi/abc/ (accessed on 20 January 2026)
ODIN II (VTR)https://docs.verilogtorouting.org/en/latest/odin/ (accessed on 20 January 2026)
GHDL-Yosys Pluginhttps://github.com/YosysHQ/yosys (accessed on 20 January 2026)
Synlighttps://github.com/chipsalliance/synlig (accessed on 20 January 2026)
Mockturtle (EPFL)https://github.com/lsils/mockturtle (accessed on 20 January 2026)
Simulation & Verification ToolsVerilatorhttps://www.veripool.org/verilator/ (accessed on 20 January 2026)
Icarus Veriloghttps://steveicarus.github.io/iverilog/ (accessed on 20 January 2026)
cocotbhttps://www.cocotb.org/ (accessed on 20 January 2026)
GTKWavehttps://gtkwave.sourceforge.net/ (accessed on 20 January 2026)
Yosys-SMTBMChttps://symbiyosys.readthedocs.io/en/latest/reference.html (accessed on 20 January 2026)
EQYhttps://github.com/YosysHQ/eqy (accessed on 20 January 2026)
CoSAhttps://github.com/cristian-mattarei/CoSA (accessed on 20 January 2026)
OpenSTAhttps://github.com/The-OpenROAD-Project/OpenSTA (accessed on 20 January 2026)
OpenTimerhttps://github.com/OpenTimer/OpenTimer (accessed on 20 January 2026)
Tatum (VTR)https://github.com/verilog-to-routing/tatum (accessed on 20 January 2026)
Physical Design Flow ToolsOpenROADhttps://theopenroadproject.org/ (accessed on 20 January 2026)
OpenLanehttps://github.com/The-OpenROAD-Project/OpenLane (accessed on 20 January 2026)
iEDAhttps://github.com/OSCC-Project/iEDA (accessed on 20 January 2026)
SiliconComphttps://github.com/siliconcompiler/siliconcompiler (accessed on 20 January 2026)
Fabricable PDKsSKY130https://github.com/gdsfactory/skywater130 (accessed on 20 January 2026)
GF180MCUhttps://github.com/google/gf180mcu-pdk (accessed on 20 January 2026)
IHP SG13G2https://github.com/IHP-GmbH/IHP-Open-PDK (accessed on 20 January 2026)
ICsprout55https://github.com/openecos-projects/icsprout55-pdk (accessed on 20 January 2026)

Jul 27, 2020

[FOSSi] OpenLANE: Open Source 130nm PDK

Join Mohamed Shalan for the 2nd talk in the Free and Open Source Silicon (FOSSi) Foundation Dial-Up series is on Tuesday 28th July, he will talk about OpenLANE on the first-in-the-industry Open Source Manufacturable SkyWater 130nm PDK

Mohamed Shalan - OpenROAD on SkyWater 130nm

Unlike the wider software world, Electronic Design Automation (EDA) open-source landscape has been fragmented for a long time, requiring significant effort and knowledge in a variety of disciplines to assemble a working ASIC flow. This has changed with projects such as Qflow and OpenROAD that aim at developing open-source toolchain for digital layout generation from RTL. OpenLane is an automated RTL to GDSII flow based on available opensource EDA tools configured/tuned for the SkyWater 130nm PDK. OpenLane main objective is to generate a clean layout from RTL designs in less than 24-hours with zero human interventions. OpenLane has been used, successfully, to tape-out a family of test chips (striVe).

Join live on YouTube on Tuesday July 28 at 16:00GMT https://lnkd.in/gCyMuPp