[Open Source Survey] From RTL to Fabrication

Emilio Isaac Baungarten-Leon

From RTL to Fabrication: Survey of Open-Source EDA Tools and PDKs

Electronics 2026, 15(5), 1048;

DOI: 10.3390/electronics15051048

* Departamento de Electromecánica, Universidad Autónoma de Guadalajara, Zapopan 45129, Mexico

Abstract: This article aims to synthesize the current ecosystem of open-source tools for Integrated Circuit (IC) design, covering the entire digital design flow from Register-Transfer Level (RTL) description to fabricable layouts. The survey categorizes and analyzes tools across major stages of design, including code-generation tools, logic synthesis, simulation, and physical design flow. Special emphasis is given to the fabricable open-source Process Design Kit (PDK), which enables the physical realization of open-hardware projects. By examining interoperability, limitations, and maturity across this toolchain, the article provides a comprehensive overview of the Electronic Design Automation (EDA) landscape and identifies the research and educational opportunities that arise from democratizing silicon design through open and reproducible workflows.

Fig: (a) IC design flow illustrating the complete process from RTL specification through logic synthesis, physical design (floorplanning, placement, clock tree synthesis, routing), verification, and final GDSII generation for fabrication. (b) FPGA design flow showing the progression from RTL description to synthesis, technology mapping, placement-and-routing on the target FPGA fabric, bitstream generation, and device configuration.

Acknowledgments: The APC was funded by Universidad Autónoma de Guadalajara (UAG), financial support provided through its Fondo Semilla. The author gratefully acknowledges the Universidad Autónoma de Guadalajara (UAG) for the financial support provided through its Fondo Semilla program, which covered the article processing charges and enabled the publication of this work. During the preparation of this manuscript, the authors utilized GPT-5.2 solely to enhance the clarity, grammar, and overall quality of the English text. The author reviewed and edited all AI-assisted content and takes full responsibility for the accuracy, originality, and integrity of the final manuscript.

Table A1. Main open-source EDA tools and their official repositories

Category	Tool	Official Link
Code-Generation Tools	PandA Bambu HLS	https://github.com/ferrandi/PandA-bambu (accessed on 20 January 2026)
	Kiwi Compiler	https://www.cl.cam.ac.uk/~djg11/kiwi/ (accessed on 20 January 2026)
	LegUp HLS	https://github.com/LegUpComputing/legup-examples?tab=readme-ov-file (accessed on 20 January 2026)
	ROCCC	http://roccc.cs.ucr.edu/ (accessed on 20 January 2026)
	PyMTL3	https://github.com/pymtl/pymtl3 (accessed on 20 January 2026)
	Chisel	https://www.chisel-lang.org/ (accessed on 20 January 2026)
	SpinalHDL	https://github.com/SpinalHDL/SpinalHDL (accessed on 20 January 2026)
	Pyverilog	https://github.com/PyHDI/Pyverilog (accessed on 20 January 2026)
	Amaranth HDL	https://github.com/amaranth-lang (accessed on 20 January 2026)
LLM-Based Code Generation	RTLCoder	https://github.com/hkust-zhiyao/RTL-Coder (accessed on 20 January 2026)
	Spec2RTL-Agent	https://cirkitly.kernex.sbs/ (accessed on 20 January 2026)
	OriGen	https://github.com/pku-liang/OriGen (accessed on 20 January 2026)
	AutoChip	https://github.com/shailja-thakur/AutoChip (accessed on 20 January 2026)
	CodeV	https://github.com/cluesmith/codev (accessed on 20 January 2026)
	VeriCoder	https://github.com/Anjiang-Wei/VeriCoder (accessed on 20 January 2026)
	StarCoder	https://github.com/bigcode-project/starcoder (accessed on 20 January 2026)
	CodeLlama	https://github.com/meta-llama/codellama (accessed on 20 January 2026)
	DeepSeek-Coder	https://github.com/deepseek-ai/DeepSeek-Coder (accessed on 20 January 2026)
	CodeQwen	https://github.com/QwenLM/qwen-code (accessed on 20 January 2026)
	Gemini	https://gemini.google.com/ (accessed on 20 January 2026)
	GPT	https://chatgpt.com/ (accessed on 20 January 2026)
	ChatEDA	https://github.com/wuhy68/ChatEDA (accessed on 20 January 2026)
Synthesis Tools	Yosys	https://yosyshq.net/yosys/ (accessed on 20 January 2026)
	ABC (Berkeley)	https://people.eecs.berkeley.edu/~alanmi/abc/ (accessed on 20 January 2026)
	ODIN II (VTR)	https://docs.verilogtorouting.org/en/latest/odin/ (accessed on 20 January 2026)
	GHDL-Yosys Plugin	https://github.com/YosysHQ/yosys (accessed on 20 January 2026)
	Synlig	https://github.com/chipsalliance/synlig (accessed on 20 January 2026)
	Mockturtle (EPFL)	https://github.com/lsils/mockturtle (accessed on 20 January 2026)
Simulation & Verification Tools	Verilator	https://www.veripool.org/verilator/ (accessed on 20 January 2026)
	Icarus Verilog	https://steveicarus.github.io/iverilog/ (accessed on 20 January 2026)
	cocotb	https://www.cocotb.org/ (accessed on 20 January 2026)
	GTKWave	https://gtkwave.sourceforge.net/ (accessed on 20 January 2026)
	Yosys-SMTBMC	https://symbiyosys.readthedocs.io/en/latest/reference.html (accessed on 20 January 2026)
	EQY	https://github.com/YosysHQ/eqy (accessed on 20 January 2026)
	CoSA	https://github.com/cristian-mattarei/CoSA (accessed on 20 January 2026)
	OpenSTA	https://github.com/The-OpenROAD-Project/OpenSTA (accessed on 20 January 2026)
	OpenTimer	https://github.com/OpenTimer/OpenTimer (accessed on 20 January 2026)
	Tatum (VTR)	https://github.com/verilog-to-routing/tatum (accessed on 20 January 2026)
Physical Design Flow Tools	OpenROAD	https://theopenroadproject.org/ (accessed on 20 January 2026)
	OpenLane	https://github.com/The-OpenROAD-Project/OpenLane (accessed on 20 January 2026)
	iEDA	https://github.com/OSCC-Project/iEDA (accessed on 20 January 2026)
	SiliconComp	https://github.com/siliconcompiler/siliconcompiler (accessed on 20 January 2026)
Fabricable PDKs	SKY130	https://github.com/gdsfactory/skywater130 (accessed on 20 January 2026)
	GF180MCU	https://github.com/google/gf180mcu-pdk (accessed on 20 January 2026)
	IHP SG13G2	https://github.com/IHP-GmbH/IHP-Open-PDK (accessed on 20 January 2026)
	ICsprout55	https://github.com/openecos-projects/icsprout55-pdk (accessed on 20 January 2026)

[paper] Insights from Basilisk

Philippe Sauter∗, Thomas Benz∗, Paul Scheffler∗ , Frank K. Gurkaynak∗ , Luca Benini∗†

Insights from Basilisk:

Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design?

arXiv:2405.04257v2 [cs.AR] 8 May 2024

* Integrated Systems Laboratory, ETH Zurich, Switzerland
† Department of Electrical, Electronic, and Information Engineering, University of Bologna, Italy

Abstract: Designing complex, multi-million-gate application specific integrated circuits requires robust and mature electronic design automation (EDA) tools. We describe our efforts in enhancing the open-source Yosys+Openroad EDA flow to implement Basilisk, a fully open-source, Linux-booting RV64GC system-onchip (SoC) design. We analyze the quality-of-results impact of our enhancements to synthesis tools, interfaces between EDA tools, logic optimization scripts, and a newly open-sourced library of optimized arithmetic macro-operators. We also introduce a streamlined physical design flow with an improved power grid and cell placement integration. Our Basilisk SoC design was taped out in IHP’s open 130 nm technology. It achieves an operating frequency of 77 MHz (51 logic levels) under typical conditions, a 2.3 improvement compared to the baseline open-source EDA flow, while also reducing logic area by 1.6. Furthermore, tool runtime was reduced by 2.5, and peak RAM usage decreased by 2.9. Through collaboration with EDA tool developers and domain experts, Basilisk establishes solid "proof of existence" for a fully open-source EDA flow used in designing a competitive multi-million-gate digital SoC.

FIG: Layout files produced by running the original Iguana flow (a) and of Basilisk (b).

TABLE: KEY METRICS OF BASILISK

Logic area (NAND2)	1.1 MGE
Logic levelsa	51 LL
Technology	130 nm IHP
Operating frequency	77 MHz
SRAM memory	172 KiB (24 macros)
Chip / core area	39 mm / 21 mm
IO count	69

^aNumber of logic gates in the longest path

Acknowledgement: We thank Alan Mishchenko, Masahiro Fujita, Giovanni De Micheli, Andrea Costamagna, Alessandro Tempia Calvino, Osama Hammad Abdel Reheem, Matt Liberty, Martin Poviser, the Yosys team, Beat Muheim, and Zerun Jiang, for their valuable contributions to the research project. We further thank all contributors to the OS EDA tools.

We are deeply grateful to IHP for their generous support and providing us with the opportunity for an open-source tapeout of this scale.
This work was supported in part through the TRISTAN (101095947) project that received funding from the HORIZON KDT-JU programme