[paper] Lambert W function for nanoscale MOSFET modeling

A. Ortiz-Conde a, V.C.P. Silva b c, P.G.D. Agopian b c, J.A. Martino b, F.J. García-Sánchez a

Some considerations about Lambert W function-based nanoscale MOSFET charge control modeling

Solid-State Electronics (2025) 109080,

DOI:10.1016/j.sse.2025.109080

a Solid-State Electronics Lab, Universidad Simón Bolívar, Caracas 1080 (VE)
b LSI/PSI/USP, Universidade de São Paulo, São Paulo (BR)
c Department of Electronic and Telecom. Eng., Universidade Estadual Paulista, São João Da Boa Vista (BR)

Abstract: The unwanted low-level doping present in supposedly undoped MOSFET channels has a significant effect on charge control and Lambert W function-based inversion charge MOSFET models, as well as on subsequent drain current models. We show that the hypothetical intrinsic MOSFET channel approximation, often used to describe a nominally undoped channel, produces significant errors, even for the low-level concentrations resulting from unintentional doping. We show that the traditional charge control model, which mathematically describes the gate voltage as the sum of one linear and one logarithmic term of the inversion charge, is only valid for the hypothetically intrinsic case. However, it may still be used for nominally undoped but unintentionally low-doped channel devices within the region of operation where the majority carriers are the dominant charge. With this in mind, we present here a better approximation of the nominally undoped MOSFET channel surface potential. We also propose an improved, modified expression that describes the gate voltage as the sum of one linear and two logarithmic terms of the inversion charge. A new approximate drain current control formulation is also proposed to account for parasitic series resistance and/or mobility degradation. The new model agrees reasonably well with measurement data from nominally undoped vertically stacked GAA Si Nano Sheet MOSFETs.

FIG: The simulated transistor structural geometry and transfer characteristics of the three TCAD simulated nanosheet devices (symbols), together with the corresponding playbacks (lines) of the traditional model and modified model.

Data availability: Data will be made available on request.

[paper] FDSOI CMOS Cryogenic SPICE Models

P. Chava1, H. Alius2, J. Bühler1, A. R. Cabrera-Galicia1, C. Degenhardt1, T. Gneiting2, M. Harff1, T. Heide3, P. Javorka4, M. Lederer5, S. Lehmann4, M. Simon5, M. Su2, P. Vliex1, S. van Waasen1,6, C. Witt7, D. Zetzsche3

Evaluation of Cryogenic Models for FDSOI CMOS Transistors

16th IEEE Workshop on Low Temperature electronics, IEEE WOLTE16, Cagliari, Italy, Jun. 3-6, 2024

DOI: 10.34734/FZJ-2024-05369

1 Central Institute of Engineering (ZEA-2), Forschungszentrum Jülich GmbH, 52428, Jülich, (D)
2 AdMOS GmbH, 72636 Frickenhausen, (D)
3 Raycics GmbH, 01069 Dresden, (D)
4 GlobalFoundries, 01109, Dresden, (D)
5 Fraunhofer Institute for Photonic Microsystems IPMS, Center Nanoelectronic Technologies (CNT), 01109, Dresden, (D)
6 Faculty of Engineering, Communication Systems, University Duisburg-Essen, 47057 Duisburg, (D)
7 GlobalFoundries, Kapeldreef 75, 3001 Leuven, (B)

Abstract: Scalable quantum computers demand innovative solutions for tackling the wiring bottleneck to control an increasing number of qubits. Cryogenic electronics based on CMOS technologies are promising candidates which can operate down to deep-cryogenic temperatures and act as a communication and control interface to the quantum layer [1,2]. However, the performance of transistors used in these circuits is altered significantly when cooling from room temperature to cryogenic temperatures, which motivates accurate cryogenic modeling of transistors. We will report on cryogenic models tailored specifically for fully depleted silicon-on-insulator (FDSOI) transistors. We performed extensive DC characterization of transistors with subsequent modeling using the BSIM-IMG 102-9.6 model, which is the first version with a built-in cryogenic extension [3]. The preliminary models effectively represent the DC device behavior from 7 K up to room temperature. These models are used in industry standard EDA and simulation software, like Cadence Spectre. With the presented cryogenic models, we will show simulations at cryogenic temperatures. We will also compare the simulation results with the measured performance of a test chip in the temperature range from 7 K up to room temperature.

FIG: Measured and modeled transfer characteristics of a short-channel nMOST at T = 7 K

with measurement setup inside the cryogenic chamber  

Acknowledgements: This work was funded by the German Federal Ministry of Education and Research (BMBF), funding program “Quantum technologies - from basic research to market”, project QSolid (Grant No. 13N16149).

En hommage à Stefan Alexandru Cserveny

 

[FOSDEM'25] OpenPDK and FOSS CAD-EDA tools

FOSDEM is a free event for software developers to meet, share ideas and collaborate, it was organized for 25th subsequent time at ULB Solbosch Campus, Brussels, Belgium, between Feb. 1-2, 2025. One of FOSDEM DevRooms (conferences sessions) "Open Hardware and CAD/CAM" was organized to review most recent developments of the printed circuit board (PCBs) design tools, circuit (ICs) designs/simulations, 3D modeling and analysis and collaborative and team-based hardware design techniques among many other related activities. The contributors and supporters of the OpenPDK Initiative showcased these remarkable developments: 

Árpád Bűrmen: "VACASK and Verilog-A Distiller - building a device library for an analog circuit simulator"

Abstract: VACASK is a novel FOSS analog circuit simulator with a clear separation between device models (i.e. equations) and circuit analyses. It is based on the state of the art KLU sparse matrix library and utilizes the OpenVAF Verilog-A compiler for building its device models from Verilog-A sources. A comparison with other FOSS analog circuit simulators is presented and the roadmap for future development is discussed. A major obstacle in development of VACASK (and every other new simulator) is the implementation of legacy device models that boils down to writing tens of thousands of lines of C code. Legacy device models are used in several older PDKs as well as in models of a large number of discrete electronic components. A novel approach to implementing these device models is proposed: a converter from SPICE3 API-based C code into modern Verilog-A code. The performance of the converted models is compared to that of native SPICE3 models. At the present the converted models can be used in VACASK and Ngspice circuit simulators as well as in any other simulator that supports Verilog-A. The limitations of the approach are discussed. Some alternative use cases for the converter are proposed and a roadmap for its future development is presented.

Holger Vogt: "ngspice - XSPICE elemental devices made available in KiCad"

Abstract: XSPICE code models have been intrgrated into ngspice since starting the ngspice project. Currently 68 device models are available, ranging from simple elements like analog gain cells or digital inverters up to complex ones like a digital state machine, SRAMs, 3D table models or interfaces to digital Verilog building blocks compiled with Verilator. The simulation with digital blocks is fast, since event based. The interface between digital and analog blocks is automated. The use of the XSPICE code models has been hampered a bit due to their specific interfaces and the lack of graphical symbols of its elements for creating user readable circuit diagrams. So I have started a project to provide XSPICE code model support via the well-known KiCad/ngspice integration. It comprises of symbol library and its assiciated device models assembled in a subcircuit model library. In the talk I will inform about its concept and status and will present some application examples 

https://forum.kicad.info/t/simulation-with-xspice-code-models/56384 https://sourceforge.net/projects/ngspice/

Felix Salfelder and Al Davis: "Verilog-AMS in Gnucap"

Abstract: Gnucap is a Free versatile and modern, modular, analog and mixed-signal simulator. Verilog-AMS is a standardized behavioural language for analog and mixed-signal systems based on the IEEE 1364-2005 industry standard, commonly known as Verilog. Gnucap was invented to advance circuit simulator technology from around 1985, at the time SPICE was developed (1973-1993) at UC Berkeley. Gnucap was released under GPLv3+ in 2001 to avoid patent issues. Today, proprietary simulators supposedly implement the most efficient algorithms yet inspired by public research from the past century. Meanwhile, the Gnucap project is making progress harvesting the breakthroughs, for use in free/libre software. To address the interoperability across circuit design tools, and across modelling domains, Verilog-AMS was created. Verilog-AMS extends traditional Verilog by analog features known from SPICE, and permits models that interact with both the digital and analog domains. The standard expertly allows for vendor-independent representations of modern circuit designs.

1 In this talk, we will explain the new revision of our proposed IEEE 1364-2005 compliant schematic interchange format, and how seamless interaction will empower FOSS EDA tools. We will outline work in progress, possibly demonstrate an application, and hint at opportunities. We will explain how the interchange will extend towards PCB design and layout

2 We will summarise new mixed signal features available in modelgen-verilog. This includes monitored analog events, as well as discrete modelling in terms of user defined primitives. We will expand on the usefulness of discrete disciplines and "connect modules", and give an update on the implementation status.

3 On the algorithmic end, we have added a plugin interface for VLSI-ready matrix solvers to the zoo. We will highlight a new solver combining temporal sparsity with the time/space efficiency of "conventional sparse" LU decomposition. We will explain why Gnucap will outpace traditional (open source) solvers on virtually all instances, both small and big circuits.

Wladek Grabinski: "The IHP OpenPK Initiative: Status and RoadMap"

Abstract: In the field of semiconductor technology, compact modeling, and IC designs, the OpenPDK Initiative provides an international platform for discussing advanced technologies, fostering collaboration among industry and academic leaders in electronic design automation (EDA). We review selected R&D topics presented at a recent event by prominent academic researchers and industrial professionals who presented and discussed innovative approaches in CAD/EDA tools, techniques including compact/SPICE modeling, and IC design that address the demands of emerging semiconductor technology applications. However, the semiconductor industry also faces many challenges in maintaining the growth of its workforce with skilled technicians and engineers. To address the increasing need for well-trained workers worldwide, we must find innovative ways to attract skilled talent and strengthen the local semiconductor workforce ecosystem. The FOSS CAD/EDA tools with the recently available open access PDKs provide a new platform to connect IC design beginners, enthusiasts and experienced mentors to benefit from the collaboration opportunities enabled by the fast-growing open-source IC design movement. The collaborative development of open-source integrated circuit (IC) designs is becoming increasingly feasible due to the rapid expansion of OpenPDKs recently offered by SkyWater, GF and IHP with an open schedule of MPW Runs for FMD-QNC project in 2024-25. This paper demonstrates the FOSS CAD/EDA contribution to the SPICE/Verilog-A modeling/standardization, compete IC design flow (Xschem, Qucs-S, ngspice, Xyce, OpenVAF, OpenEMS, Magic, kLayout, OpenRoad), in addition selected, open-source examples of analog/RF and digital IC designs will be presented.

 

ACM2 for IHP-SG13 OpenPDK

ACM2 MOSFET model examples for IHP-SG13 OpenPDK

The ACM2V0 model [1,2] was compared with measurements of the 130 nm BiCMOS open-source PDK IHP-SG13G2, as well as with MOS model provided by the PDK. Plots for IDvs.VG@VD= 0.05, 0.6 and 1.2 V and IDvs.VD@VG=0.185, 0.7 and 1.35 V W/L = 10 um / 120 nm

REFERENCE:

[1] Advanced Compact MOSFET model 2 (ACM2) https://github.com/ACMmodel/MOSFET_model

[2] Neto, Deni Germano Alves, Mohamed Khalil Bouchoucha, Gabriel Maranhão, Manuel J. Barragan, Márcio Cherem Schneider, Andreia Cathelin, Sylvain Bourdel, and Carlos Galup-Montoro. "Design-oriented single-piece 5-DC-parameter MOSFET model." IEEE Access (2024) doi:10.1109/ACCESS.2024.3417316

[paper] SPICE Modeling of a Radiation Sensor

Miloš Marjanović 1, Stefan D. Ilić 2, Sandra Veljković 1, Nikola Mitrović 1, Umutcan Gurer 3, Ozan Yilmaz 3, Aysegul Kahraman 4, Aliekber Aktag 3, Huseyin Karacali 3, Erhan Budak 3, Danijel Danković 1, Goran Ristić 1 and Ercan Yilmaz 3

The SPICE Modeling of a Radiation Sensor Based on a MOSFET

with a Dielectric HfO2/SiO2 Double-Layer

Sensors 2025, 25(2), 546; DOI:10.3390/s25020546

1 Department of Microelectronics, Faculty of Electronic Engineering, University of Niš, Serbia
2 Center of Microelectronic Technologies, Institute of Chemistry, Technology and Metallurgy, University of Belgrade, Serbia
3 Faculty of Arts and Sciences, Bolu Abant Izzet Baysal University, Turkey
4 Department of Physics, Faculty of Arts and Sciences, Bursa Uludag University, Turkey

Abstract: We report on a procedure for extracting the SPICE model parameters of a RADFET sensor with a dielectric HfO2/SiO2 double-layer. RADFETs, traditionally fabricated as PMOS transistors with SiO2, are enhanced by incorporating high-k dielectric materials such as HfO2 to reduce oxide thickness in modern radiation sensors. The fabrication steps of the sensor are outlined, and model parameters, including the threshold voltage and transconductance, are extracted based on experimental data. Experimental setups for measuring electrical characteristics and irradiation are described, and a method for determining model parameters dependent on the accumulated dose is provided. A SPICE model card is proposed, including parameters for two dielectric thicknesses: (30/10) nm and (40/5) nm. The sensitivities of the sensors are 1.685mV/Gy and 0.78mV/Gy, respectively. The model is calibrated for doses up to 20Gy, and good agreement between experimental and simulation results validates the proposed model.

FIG: (a) Block diagram of the radiation source setup; 

(b) radiation setup in the TENMAK lab.

The corresponding SPICE model card is presented below:

.MODEL RADFET PMOS VTO={if(TYPE==1,-0.493-(1.54e-3*DOSE),-0.65433-(7.54E-4*DOSE))}

+KP={if(TYPE==1,8.897e-6-(1.493e-8*DOSE),1.14E-5-(2.511E-9*DOSE))} L=50e-6 W=600e-6

+TPG=0 LAMBDA={if(TYPE==1,3.901E-2-(2.165E-4*DOSE),2.0115E-2-(1.8575E-4*DOSE))}

Acknowledgements: This research was funded by North Atlantic Treaty Organization (NATO) SPS MYP under grant number G5974, by the project “High-k Dielectric RADFET for Detection of RN Treats”, and supported by the Ministry of Science, Technological Development and Innovation of the Republic of Serbia [grant number 451-03-65/2024-03/200102 and grant number 451-03-66/2024-03/200026].

[CI Inovador] OpenPDK Introduction

INOVA-ME: Curso de Capacitação, Inovação, Gestão e Empreendedorismo em Microeletrônica

INOVA-ME é um dos polos de capacitação do Programa CI Inovador financiado pelo MCTI e coordenado pela Softex , executado pelo Instituto de Informática da Universidade Federal do Rio Grande do Sul (INF-UFRGS).

The OpenPDK Introduction is part of the CI Inovador course, 

scheduled for January 24, 2025, from 13:30 to 15:00 BRT.

The conference call platform is MCONF, accessible via the following link: https://mconf.ufrgs.br/webconf/inova-me

Agenda:

---

1. General Introduction and Technical Presentation (1 hour)

Wladek Grabinski: General introduction to FOSS EDA/CAD and OpenPDK (20-25 minutes)

Dr. Wladek Grabinski, a distinguished expert with over 30 years of international experience in semiconductor R&D, compact modeling, and custom IC design. Currently, leading engineering R&D at GMC Consulting, and supports IHP OpenPDK Initiative. Dr. Grabinski has worked with renowned institutions such as EPFL, Motorola, and Freescale. He is an accomplished author of multiple books on analog/RF modeling and a recognized leader in developing advanced SPICE models for nanoscale CMOS technologies. Dr. Grabinski's contributions continue to shape the field of analog and RF IC design in the OpenPDK domain.

Krzysztof Herman: Technical OpenPDK presentation, 

including design demos and an IHP overview (20-25 minutes)

Dr. Krzysztof Herman, a research associate specializing in OpenPDK development at IHP in Germany. With over a decade of experience, including roles as a professor and researcher in Europe and Latin America, Dr. Herman has expertise spanning telecommunications, ASIC design, and FPGA development. He has also contributed to Antarctic and polar research expeditions, showcasing his multidisciplinary approach and dedication to advancing both science and technology.

Q&A: 10 minutes

2. OpenPDK Brazil Discussion and Demonstration (30 minutes)

Francisco Brito: Real chip design demonstration using IHP OpenPDK (10-12 minutes)

Dr. Francisco Brito Filho, UFERSA, Professor and Head of the LIEB/LAMERF Research Labs. Dr. Brito holds a PhD in RF Microelectronics and has extensive expertise in RF/AMS IC design, instrumentation, and biomedical engineering. With experience in academia, industry, and entrepreneurship, Dr. Brito has worked on innovative projects ranging from CMOS-based RFICs to advanced biomedical equipment. His leadership and technical excellence continue to drive impactful research and development in microelectronics. He is already teaching microelectronics classes using OpenPDK and OpenSource tools.

Q&A: 3 minutes

Juan Brito: OpenPDK Brazil Discussion (10-12 minutes)

Dr. Juan Brito has over two decades in Semiconductors and Integrated Circuits, deep expertise in device engineering, analog design, and advanced IC testing. Dr. Brito has passion for continuous development is evidenced by contributions to academic publications and involvement in international student exchange programs. He is lookin for new challenges that leverage technical and managerial expertise to drive innovation and sustainable growth in the semiconductor industry particularly in the OpenPDK domain.

Q&A: 3 minutes

[paper] Nanowire Biosensor Analytical Model

Ashkhen Yesayan, Aleksandr Grabski, Farzan Jazaeri, Jean-Michel Sallese

Design-Oriented Analytical Model for Nanowire Biosensors Including Dynamic Aspects

IEEE TED (2025) DOI 10.1109/TED.2025.3526113

Abstract: Nanowire Field Effect Transistor (NWFET) biosensors are known to be highly sensitivity devices that can detect extremely low concentrations of biomolecules. In this paper, we present an analytical model alongside with numerical simulations to calculate the sensitivity of NWFET biosensors. The model accounts for biosensing dynamics as well as diffusion of ions in the solution and across the functionalized layer. The signal-to-noise ratio is also estimated, which gives a lower limit in terms of sensitivity. The model is physics based and is validated against a commercial multiphysics simulations and experimental data. It predicts the bio-sensitivity down to femtomolar concentration of biomolecules without any fitting parameter.

FIG: Schematic structure of device (a), the charge distribution in theoretical model (b) 

and Si NWFET sensitivity simulated with presented model (c)

Acknowledgement: This work was supported by the Science Committee of RA, in the frames of the research project No:21T-2B321.

SwissChips: foster the Swiss semiconductor ecosystem

SwissChips is an inital three-year transitional measure jointly led by the Swiss Center for Electronics and Microtechnology (CSEM), EPFL and ETH, aimed to maintain and secure a strong position of Swiss researchers and research infrastructure in the strategically important areas of semiconductor technologies, microelectronics, and more specifically cutting-edge integrated circuit (IC) design within the European landscape [read more...]

[paper] Spatz: open-source RISC-V compact VPU

Matteo Perotti, Samuel Riedel, Matheus Cavalcante and Luca Benini^1,2

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency

arXiv:2309.10137v2 [cs.AR] 9 Jan 2025

1 IIS, ETH Zurich (CH)
2 DEI, Uni. Bologna (IT)

Abstract: The ever-increasing computational and storage requirements of modern applications and the slowdown of technology scaling pose major challenges to designing and implementing efficient computer architectures. To mitigate the bottlenecks of typical processor-based architectures on both the instruction and data sides of the memory, we present Spatz, a compact 64-bit floating-point-capable vector processor based on RISC-V’s Vector Extension Zve64d. Using Spatz as the main Processing Element (PE), we design an open-source dual-core vector processor architecture based on a modular and scalable cluster sharing a Scratchpad Memory (SCM). Unlike typical vector processors, whose Vector Register Files (VRFs) are hundreds of KiB large, we prove that Spatz can achieve peak energy efficiency with a latch-based VRF of only 2 KiB. An implementation of the Spatz-based cluster in GlobalFoundries’ 12LPP process with eight double-precision Floating Point Units (FPUs) achieves an FPU utilization just 3.4% lower than the ideal upper bound on a double-precision, floating-point matrix multiplication. The cluster reaches 7.7 FMA/cycle, corresponding to 15.7 GFLOPSDP and 95.7 GFLOPSDP/W at 1 GHz and nominal operating conditions (TT, 0.80 V, 25 °C), with more than 55% of the power spent on the FPUs. Furthermore, the optimally-balanced Spatz-based cluster reaches a 95.0% FPU utilization (7.6 FMA/cycle), 15.2 GFLOPSDP, and 99.3 GFLOPSDP/W (61% of the power spent in the FPU) on a 2D workload with a 7 × 7 kernel, resulting in an outstanding area/energy efficiency of 171 GFLOPSDP/W/mm2. At equi-area, the computing cluster built upon compact vector processors reaches a 30% higher energy efficiency than a cluster with the same FPU count built upon scalar cores specialized for streambased floating-point computation.

Fig: Placed-and-routed Spatz-based shared-L1 cluster, implemented as a 737 μm × 1003 μm block. The cluster’s main blocks are highlighted: namely the Snitch cores, VRFs, IPUs, FPUs, L1 SPM, and I$.

Acknowledgment: This work was supported in part through the TRISTAN (#101095947) and the ISOLDE (#101112274) projects, both funded through the Chips Joint Undertaking (CHIPS JU) of the European Union’s Horizon Europe’s research and innovation programme and its members.

[book] From Code to Chip

Jakob Ratschenberger and Harald Pretl

From Code to Chip:

Open-Source Automated Analog Layout Design

pp: XV, 120 Publisher: Springer Cham (10 January 2025)

eBook ISBN 978-3-031-68562-0

This book shows how the layout of an analog circuit can be automatically generated in a fully open-source way. Based on an exemplary design flow, it introduces and explains the necessary steps for transforming a SPICE netlist into a layout, which can be inspected by the open-source layout editor Magic VLSI. This is done by using the industry’s first open-source process design kit SKY130. Furthermore, the implementation of the design flow in the programming language Python is available as open-source on GitHub. 

Authors' Affiliations

Johannes Kepler University, Linz, Austria

Table of contents (8 chapters)

• Front Matter pp. i-xv
• Download chapter PDF 
• Introduction pp. 1-4
• Theoretical Basics pp. 5-13
• Circuit Capturing pp. 15-36
• PDK—Design Rule Capturing pp. 37-41
• Placement pp. 43-55
• Routing pp. 57-71
• Experimental Results pp. 73-99
• Outlook pp. 101-103
• Back Matter pp. 105-120

 

[paper] Compact Model of Linear Passive IPD

Zhang, Zijian

Compact Model of Linear Passive Integrated Photonics Device

for Photon Design Automation

arXiv preprint: 2501.06774 (2025)

1 University of Electronic Science and Technology of China, Chengdu, 611731, China

Abstract: As integrated photonic systems grow in scale and complexity, Photonic Design Automation (PDA) tools and Process Design Kits (PDKs) have become increasingly important for layout and simulation. However, fixed PDKs often fail to meet the rising demand for customization, compelling designers to spend significant time on geometry optimization using FDTD, EME, and BPM simulations. To address this challenge, we propose a data-driven Eigenmode Propagation Method (DEPM) based on the unitary evolution of optical waveguides, along with a compact model derived from intrinsic waveguide Hamiltonians. The relevant parameters are extracted via complex coupled-mode theory. Once constructed, the compact model enables millisecond-scale simulations that achieve accuracy on par with 3D-FDTD, within the model’s valid scope. Moreover, this method can swiftly evaluate the effects of manufacturing variations on device and system performance, including both random phase errors and polarization-sensitive components. The data-driven EPM thus provides an efficient and flexible solution for future photonic design automation, promising further advancements in integrated photonic technologies.

Fig: Photon design automation workflow based on compact model

of linear passive optical waveguide

Supplementary information:

The time evaluations were conducted on a system equipped with an Intel i9-10850K processor, 64 GB DDR4 memory, and NVIDIA Quadro RTX 5000 professional graphics processor.

[paper] Strategic Thinking on Open-Source PDK

(Medium link)

Written by Jun-ichi OKAMURA

IEEE Senior member (Bio)

In 1990, NHK hailed Japan as an "lectronic powerhouse," spotlighting the semiconductor industry. Now, three decades later, the spotlight has swung back onto semiconductors - though the star this time is cutting-edge manufacturing technology. In this piece, however, The Author’d like to shift the focus to the design side of semiconductors. This article follows in the footsteps of several earlier posts: "The Tale of PDKs, Past and Present" posted Dec. 3, 2023; "A Qualitative Cost Analysis of the Semiconductor Business" posted Aug.1, 2024; and "Semiconductors We Want to Make, Semiconductors We Want to Use" posted Dec. 23, 2024. I’m grateful that these pieces still receive steady traffic, and The Author hopes they’ve helped broaden my understanding of the design aspects of semiconductors for those in the industry.

This time, under the title “Strategic Thinking on Open-Source PDK (Process Design Kit),” The Author aims to explain key points about open-source PDKs clearly. The discussion doesn’t stop at semiconductor designers — it also addresses perspectives relevant to foundries (semiconductor manufacturing service providers) and those planning semiconductor-related businesses. The Author hopes you’ll find it an engaging read and a helpful resource.

Note: The views expressed here are authors's own, based on past work experience, and do not represent any organization.

[paper] SPICE Compact FLASH Memory Model

Jung Rae Cho 1, Donghyun Ryu 2,3, Donguk Kim1, Wonjung Kim1, Yeonwoo Kim 2,3, Changwook Kim 1, Yoon Kim 4, Myounggon Kang 5, Jiyong Woo 6, and Dae Hwan Kim 1

Physics-Based SPICE-Compatible Compact Model of FLASH Memory 

With Poly-Si Channel for Computing-in-Memory Applications

in IEEE Journal of the Electron Devices Society, vol. 13, pp. 1-7, 2025

doi: 10.1109/JEDS.2024.3511581.

1 School of Electrical Engineering, Kookmin University, Seoul 02707, South Korea
2 Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea
3 Inter-University Semiconductor Research Center, Seoul National University, Seoul 08826, South Korea
4 School of Electrical and Computer Engineering, University of Seoul, Seoul 02504, South Korea
5 School of Advanced Fusion Studies, University of Seoul, Seoul 02504, South Korea
6 School of Electronic and Electrical Engineering, Kyungpook National University, Daegu 41566, South Korea

ABSTRACT: Recently, three-dimensional FLASH memory with multi-level cell characteristics has attracted increasing attention to enhance the capabilities of artificial intelligence (AI) by leveraging computingin-memory (CIM) systems. The focus is to maximize the computing performance and design FLASH memory suitable for various AI algorithms, where the memory must achieve a highly controllable multi-level threshold voltage (VT). Therefore, we developed a SPICE compact model that can rapidly simulate charge trap FLASH cells for CIM to identify optimal programming conditions. SPICE simulation results of the transfer characteristics are in good agreement with the results of experimentally fabricated FLASH memory, showing a low error rate of 10%. The model was also validated against the results obtained from the TCAD tool, showing that a consistent VT change was computed in a shorter time than that required using TCAD. Then, the developed model was used to comprehensively investigate how single or multiple gate voltage (VG) pulses affect VT. Moreover, considering recent FLASH memory fabrication processes, we found that grain boundaries in polycrystalline silicon channel materials can be involved in deteriorating gate controllability. Therefore, optimizing the pulse scheme by correcting potential errors identified in advance through fast SPICE simulation can enable the accurate achievement of the specific analog states of the FLASH cells of the CIM architecture, boosting computing performance.

FIG: Device structure of FLASH memory cell for TCAD Sentaurus simulation and its transfer characteristics of FLASH memory obtained from measurement and SPICE simulation.

Acknowledgements: This work was supported in part by the Institute of Information and Communications Technology Planning and Evaluation (IITP) funded by the Korea Government (MSIT) under Grant 2021-0-01764-001; in part by the National Research Foundation of Korea (NRF) funded by the Korean Government (MSIT) under Grant RS-2023-00208661; in part by the Ministry of Trade, Industry & Energy (MOTIE) under Grant 1415187390; in part by the Korea Semiconductor Research Consortium (KSRC) support program for the Development of the Future Semiconductor Device under Grant 00231985; and in part by the 2023 Research Fund of Kookmin University, South Korea. The work of Jiyong Woo was supported by the National Research and Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT under Grant RS-2023-00258227.

[paper] Optoelectronic device library containing multiple Verilog-A models

Guanliang Chen, Zhigang Song and Xinhe Zheng

Optoelectronic device library containing multiple Verilog-A models

Sci Rep 15, 1115 (2025) doi: 10.1038/s41598-024-80150-6

1 Key Laboratory of Solid-State Optoelectronics Information Technology, Institute of Semiconductors, Chinese Academy of Sciences, Beijing, 100083, China
2 Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing, 100049, China
3 School of Mathematics and Physics, Beijing Key Laboratory for Magneto-Photoelectrical Composite and Interface Science, University of Science and Technology Beijing, Beijing, 100083, China

Abstract: The advancement of the optoelectronic fusion industry has escalated the demands for optoelectronic simulation, yet a comprehensive model library remains unavailable for chip designers. We have utilized the hardware description language Verilog-A to develop an extensive optoelectronic device model library, featuring a full range of device types, unified interfaces, and the capability to simulate the physical effects of devices. Establishing this model library is intended to alleviate the workload of chip designers and reduce development costs.

TAB: Comparison with Verilog-A model library and others

FIG: Schematic diagram of a compact Verilog-A model of VCSEL and its DC test results

[mos-ak] [Online Publications] 17th International MOS-AK Workshop Silicon Valley, December 11, 2024

17th International MOS-AK Workshop 

Silicon Valley, December 11, 2024

   

Online MOS-AK Workshop Publications

The 17th International MOS-AK Workshop on Compact/SPICE Modeling was held online on Dec.11, 2024, in the timeframe of IEDM and Q4 CMC Meetings with Keysight Technologies organization support. The MOS-AK workshop publications [1-9], with individually assigned DOI numbers, are available online:

<https://www.mos-ak.org/silicon_valley_2024/>

-- W.Grabinski on the behalf of International MOS-AK Committee

REF:

[1] L. Ma, "What's New in Keysight Device Modeling 2025", presented at the 17th International MOS-AK Workshop (MOS-AK), Remote/Online Silicon Valley, Dec. 11, 2024. doi: 10.5281/zenodo.14621746
[2] P. M. Lee, "Si2 Compact Model Coalition", presented at the 17th International MOS-AK Workshop (MOS-AK), Remote/Online Silicon Valley, Dec. 11, 2024. doi: 10.5281/zenodo.14621935.
[3] Á. Bűrmen, "OpenVAF - status update, ecosystem, and a roadmap", presented at the 17th International MOS-AK Workshop (MOS-AK), Remote/Online Silicon Valley, Dec. 11, 2024. doi: 10.5281/zenodo.14622027.
[4] H. Agarwal and G. Pahwa, "A Wrapper Model for ESD-FET Simulation and Analysis", presented at the 17th International MOS-AK Workshop (MOS-AK), Remote/Online Silicon Valley, Dec. 11, 2024. doi: 10.5281/zenodo.14622109.
[5] T. R. Ratier, J.-C. Delvenne, D. Flandre, L. Van Brandt, "Compact Modelling of Memristors Toward Analog Neuromorphic Circuit Simulations", presented at the 17th International MOS-AK Workshop (MOS-AK), Remote/Online Silicon Valley, Dec. 11, 2024. doi: 10.5281/zenodo.14623688.
[6] H. Dias Gilo, I. Alves Salesand, F. de Assis Brito Filho, "Inductor Modeling and Generation Flow for Verified RFIC Layouts Using Open-Source PDKs", presented at the 17th International MOS-AK Workshop (MOS-AK), Remote/Line Silicon Valley, Dec. 11, 2024. doi: 10.5281/zenodo.14624239.
[7] Q. Chen, V. Kilchytska, E. Bestelink, R. A. Sporea, D. Flandre, L. Van Brandt, "Characterization and modelling of low-frequency noise in polysilicon thin-film source-gated transistors from subthreshold to saturation", presented at the 17th International MOS-AK Workshop (MOS-AK), Remote/Online Silicon Valley, Dec. 11, 2024. doi: 10.5281/zenodo.14624309.
[8] B. Murmann, "Gm/ID-Based Analog Circuit Sizing Using Ngspice and Python", presented at the 17th International MOS-AK Workshop (MOS-AK), Remote/Online Silicon Valley, Dec. 11, 2024. doi: 10.5281/zenodo.14624372.
[9] Roberto Murphy, "Semiconductor R&D in Mexico" presented at the 17th International MOS-AK Workshop (MOS-AK), Remote/Online Silicon Valley, Dec. 11, 2024. doi:10.5281/zenodo.14529798

WG090125

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[paper] MOSFET-Based Voltage Reference Circuits

Moisello, Elisabetta, Edoardo Bonizzoni, and Piero Malcovati

MOSFET-Based Voltage Reference Circuits in the Last Decade: A Review

Micromachines 15, no. 12 (2024): 1504

Abstract: Voltage reference circuits are a basic building block in most integrated microsystems, covering a wide spectrum of applications. Hence, they constitute a subject of great interest for the entire microelectronics community. MOSFET-based solutions, in particular, have emerged as the implementation of choice for realizing voltage reference circuits, given the supply voltage scaling and the ever-lower power consumption specifications in various applications. For these reasons, this paper aims to review MOSFET-based voltage reference circuits, illustrating their principles of operation, as well as presenting a detailed overview of the state-of-the-art, in order to paint an accurate picture of the encountered challenges and proposed solutions found in the field in the last decade, thus providing a starting point for future research in the field.

FIG: Schematic of a generic threshold voltage-based MOSFET reference circuit

and graphical representation of a transistor ZTC point.

SSCS PICO Chronicle

Mirjana Videnovic-Misic, Harald Pretl, Ali Sabir, Zonghao (Chris) Li, 

and Sadayuki Yoshitomi

SSCS PICO Chronicles: news from the open source community

Date of current version: 14 November 2023

DOI: 10.1109/MSSC.2023.3315888

The Growing Activity of Open Source Chip Design in Japan

The Chipathon 2023 Team Japan consists of 12 volunteers from industry and academia. Since the team members are located in different parts of Japan, the team will be working remotely to design the project. On 4 August, they held a kickoff meeting where the members, who had been working together on Slack, gathered for the first time in person. Although many of the team members have no tape-out experience, they are all truly interested in IC design. The leader of Team Japan is Prof. Akira Tsuchiya at the University of Shiga in Japan (FIG).

Prof. Tsuchiya has been working on open source IC design and has been a volunteer member of the SSCS Chipathon since October 2022. He has promoted open source IC design and SSCS PICO activities in Japan. He held several hands-on events, for example, at the summer camp of the IE- ICE ICD in 2022. Also, he gave several talks about open source IC design and his research on analog synthesis in domestic conferences. And now, he has recruited members and applied to the latest Chipathon. Let’s look forward to the activities of the new members of “Team Japan.”

FIG: Prof. Akira Tsuchiya, an associate professor of the University of Shiga prefecture, 

Japan, and a snapshot of the kickoff meeting (hybrid) of the Chipathon 2023 Japan team