[IEEE EDS DL] Multifunctional materials for emerging optoelectronic technologies

IEEE EDS Distinguished Lecture

Hawaii Section Jt. Chapter, ED15/SSC37

December 19 @ 6:30 pm - 8:00 pm

Room: 244, Bldg: Holmes Hall, 2540 Dole St, Honolulu

Hawaii, United States, 96822

Dr. Federico Rosei from the University of Trieste will be presenting a Distinguished Lecturer Seminar titled "Multifunctional materials for emerging optoelectronic technologies" on Friday December 19th at 6:30PM. RSVP one week in advance for a headcount on food [register]

Abstract: functionalities. Such systems are then used as building blocks for the fabrication of various emerging technologies. In particular, nanostructured materials synthesized via the bottom–up approach present an opportunity for future generation low cost manufacturing of devices. We focus in particular on recent developments in solar technologies that aim to address the energy challenge, including third generation photovoltaics, solar hydrogen production, luminescent solar concentrators and other optoelectronic devices. 

Bio: Federico Rosei (MSc (1996) and PhD (2001) from the University of Rome “La Sapienza”) holds the Chair of Industrial Chemistry at the Department of Chemical and Pharmaceutical Sciences, University of Trieste since March 2023. Previously he was Full Professor at the Centre Énergie, Matériaux et Télécommunications, Institut National de la Recherche Scientifique, Varennes (QC) Canada, where he served as Director (07/2011–03/2019). He held the Canada Research Chair (Junior) in Nanostructured Organic and Inorganic Materials (2003–2013) and the Canada Research Chair (Senior) in Nanostructured Materials (2016–2023) and the UNESCO Chair in Materials and Technologies for Energy Conversion, Saving and Storage (2013–2023).

[paper] Compact Wide-Band Antenna

A. Anand Babu, K. Thenmalar

Design and Evaluation of a Compact Wide-Band Antenna for Wearable Wireless Applications

Tehnički vjesnik 32, 6(2025), 2437-2442

Original scientific paper DOI: 10.17559/TV-20241128002156

ECE, Vivekanandha College of Technology, Tiruchengode, Tamil Nadu, India
EEE, Vivekanandha College of Engineering for Women, Tiruchengode, Tamil Nadu, India

Abstract: This article presents a compact wide-band antenna designed for emerging wireless applications. The antenna utilizes a fiberglass-reinforced (FR4) substrate material with a thickness of 1.6 mm as its base. By varying the length and side edge dimensions of the antenna element, the design achieves a wide operational bandwidth ranging from 3.2 to 3.8 GHz, covering all new radio bands. Experimental optimization of various parameters has been conducted to ensure precise tuning within the desired frequency range. The antenna exhibits a uniform radiation pattern across its operating band, ensuring stable performance. Specific Absorption Rate (SAR) evaluations, conducted as per the Federal Communications Commission (FCC) guidelines, confirm the SAR values remain within the prescribed safety limit of 1.6 W/kg when the antenna is positioned on a human phantom model. The proposed antenna also demonstrates high radiation efficiency and peak gain, making it suitable for wearable applications where compact size and reliable performance are critical. This innovative design addresses the growing demand for wide-band antennas in wireless communication systems, emphasizing safety, efficiency, and adaptability for wearable technologies.

Fig: Electric field distribution over the radiating circle at (a) 3.45 GHz; (b) 3.7 GHz

(c) - (d) fabricated antenna images

[Free Session] Tokai Rika OpenPDK

Tokai Rika Shuttle Open PDK Commentary Free Session

Saturday, December 13, 2025 13:00~17:00 [and online]

WeWork Hibiya FORT TOWER 9th Floor, Conference Room 9R

1-1 Nishi-Shimbashi, Minato-ku, Tokyo

Time	Speaker	Topic
12:50	ISHI Club	1F Gathering
13:00	ISHI Club	Opening
13:00-13:30	OpenSUSI	Overview of Tokai Rika Shuttle PDK and future plans
13:30-14:30	jun1okamura	Outline of the production of DRC and LVS of Tokai Rika Shuttle PDK and explanation of contents
14:30-15:00	OpenSUSI	Break & Information Exchange
15:00-15:30	Mitch Bailey	Detailed explanation of LVS (Japanese lecture)
15:30-16:00	Hota (SIG's Playground)	How to 🚶 walk through open source PDK: "What is PDK in the first place?" "Where do you want to "read" PDK? "If you want to make your own PDK, where do you start?" and "Examples of what you have done so far".
16:00-16:30	OpenSUSI	PDK Conversation: jun1okamura x Hota x Mitch Bailey: Mr. Hota, an expert in commercial PDK development at a major domestic company, and Mitch Bailey, an expert in open PDK who has been performing structural checks and PDK maintenance of GDS submitted by eFabless, etc.
16:30-17:00	OpenSUSI	PDK Conversation / Honest Edition (No more online streaming will be done from now on): Continuing from the above, we plan to talk about things that cannot be said publicly. In a sense, this may be the real thing.
17:00	ISHI Club	Closing

Discord invitation link 

https://discord.gg/Sj47dJk8x7 

https://discord.gg/RwAWF5mZSR

[Book] Essential Semiconductor Physics

Essential Semiconductor Physics

Mark Lundstrom (Purdue University, USA)

New Era Electronics: A Lecture Notes Series

Pages: 424; October 2025

https://doi.org/10.1142/14454

This book is the fourth volume in the New Era Electronics lecture notes series, a compilation of volumes defining the important concepts tied to the electronics transition happening in the 21st century.

The lectures in this volume are about the underlying physics that makes semiconductor devices possible. The treatment is physical and intuitive; the text is descriptive, not heavily mathematical. The lectures are designed to be broadly accessible to students in science or engineering and to working engineers. They present an electrical engineering perspective, but those in other fields may find them a useful introduction to the approach that has guided the development of semiconductor technology for more than 75 years.

For those who use semiconductor devices, these lectures provide an understanding of the physics that underlies their operation. For those developing semiconductor technologies, these lectures provide a starting point for diving deeper into the physics, chemistry, and materials science relevant to semiconductors. Those who have taken advanced courses will see how specific topics fit into a broader framework. 

Book Sections

Front Matter; pp. i–xvi

Part 1: Materials Properties and Doping

• Lecture 1: Energy Levels to Energy Bands; pp. 3–16
• Lecture 2: Crystalline, Polycrystalline, and Amorphous Semiconductors; pp. 17–27
• Lecture 3: Miller Indices; pp. 29–39
• Lecture 4: Properties of Common Semiconductors; pp. 41–46
• Lecture 5: Free Carriers in Semiconductors; pp. 47–56
• Lecture 6: Doping; pp. 57–75

Part 2: Rudiments of Quantum Mechanics

• Lecture 7: The Wave Equation; pp. 79–99
• Lecture 8: Quantum Confinement; pp. 101–116
• Lecture 9: Quantum Tunneling and Reflection; pp. 117–129
• Lecture 10: Electron Waves in Crystals; pp. 131–145
• Lecture 11: Density of States; pp. 147–164

Part 3: Equilibrium Carrier Concentrations

• Lecture 12: The Fermi Function; pp. 167–177
• Lecture 13: Fermi-Dirac Integrals; pp. 179–190
• Lecture 14: Carrier Concentration vs. Fermi Level; pp. 191–203
• Lecture 15: Carrier Concentration vs. Doping Density; pp. 205–213
• Lecture 16: Carrier Concentration vs. Temperature; pp. 215–228

Part 4: Carrier Transport, Recombination, and Generation

• Lecture 17: Current Equation; pp. 231–250
• Lecture 18: Drift Current; pp. 251–270
• Lecture 19: Diffusion Current; pp. 271–280
• Lecture 20: Drift-Diffusion Equation; pp. 281–288
• Lecture 21: Carrier Recombination; pp. 289–308
• Lecture 22: Carrier Generation; pp. 309–323

Part 5: The Semiconductor Equations

• Lecture 23: The Semiconductor Equations; pp. 327–342
• Lecture 24: Energy Band Diagrams; pp. 343–361
• Lecture 25: Quasi-Fermi Levels; pp. 363–374
• Lecture 26: Minority Carrier Diffusion Equation; pp. 375–396

Back Matter; pp. 397–406

[paper] 28 GHz Wireless Channel for a Quantum Computer at 4K

Ama Bandara∗, Viviana Centritto Arrojo∗, Heqi Deng†, Masoud Babaie†, Fabio Sebastiano†, Edoardo Charbon‡, Evgenii Vinogradov∗, Eduard Alarcon∗, Sergi Abadal∗

28 GHz Wireless Channel Characterization for a Quantum Computer Cryostat at 4 Kelvin

arXiv:2510.16962v1 [quant-ph] 19 Oct 2025

∗Nanonetworking Center in Catalunya, Universitat Politecnica de Catalunya, Barcelona (SP)
† Delft University of Technology (NL)
‡ Ecole Polytechnique F ́ed ́erale de Lausanne (EPFL, CH) 

Abstract: The scalability of quantum computing systems is constrained by the wiring complexity and thermal load introduced by dense wiring for control, readout and synchronization at cryogenic temperatures. To address this challenge, we explore the feasibility of wireless communication within a cryostat for a multi-core quantum computer, focusing on wireless channel characterization at cryogenic temperatures. We propose to place on-chip differential dipole antennas within the cryostat, designed to operate at 28 GHz in temperatures as low as 4 K. We model the antennas inside a realistic cryostat and, using full-wave electromagnetic simulations, we analyze impedance matching, spatial field distribution, and energy reverberation due to metallic structures. The wireless channel is characterized through measured channel impulse response (CIR) across multiple receiver antenna positions. The results demonstrate potential for reliable shortrange communication with high Signal-to-Noise Ratio (SNR) and limited sensitivity to positional variation, at the cost of nonnegligible delay spread, due to significant multipath effects.

Fig: Spatial distribution of the electrical field across the cryostat as observed in the cross-section, 
general top view, and top view at the plane of the antennas.

Acknowledgements: Authors gratefully acknowledge funding from the European Commission via projects with GA 101042080 (WINC) and 101099697 (QUADRATURE).

[IEEE EDS MQ] Trends and Challenges in Microelectronics

IEEE EDS MQ “Trends and Challenges in Microelectronics”

Monday, October 13th, 2025

FACULTY OF ELECTRONIC ENGINEERING

University of Niš

Aleksandra Medvedeva 4, Niš, Serbia

8:00 Registration

8:30   Introductory Remarks and Opening Address

D. Danković, University of Niš, Serbia
Z. Marinković, University of Niš, Serbia

Session I: Chairmen: T. Grasser, V. Davidović

8:45   Device Engineering in E.V.E. Era for Sustainable Nanoelectronics and Nanosystems

S. Deleonibus; CEA/LETI, France

9:10 Neuromorphic Technologies for Autonomous Intelligent Systems at the Edge
[online] A. M. Ionescu; Swiss Federal Institute of Technology, Switzerland

9:30 Coffee break

9:40 Contacts at the Nanoscale and for Nanomaterials

H. Wong; University of Hong Kong, Hong Kong

10:05 Unlocking the Potential of Multifunctional Devices

[online] N. El-Atab; KAUST Saudi Arabia

10:25 Coffee break

Session II: Chairmen: H. Wong, D. Danković

10:35 Steep-slope Devices: Prospects and Challenges

E. Gnani; University of Bologna, Italy

11:00 Modeling FinFETs, Nanowires and Stacked Nanosheets with Temperature

[online] A. Cerdeira; CINVESTAV-IPN, Mexico

11:20 Coffee break

11:30 The IHP OpenPDK Initiative: RoadMap Update

W. Grabinski; IEEE EDS R8 Chair

11:55 A Review of Lambert’s W Function Utilization in Nanodevice Modeling

[online]A. Ortiz-Conde; University Simon Bolivar, Venezuela

12:15 Coffee break

12:25 Benchmarking Insulators for Devices Based on 2D Materials

T. Grasser; Technical University of Vienna, Austria

 

[Internship] Open Source CAD Design Flows

A great opportunity at CEA-Leti in Grenoble, France! This 6-month internship focuses on open source CAD design flows with related PDK, targeting final-year engineering or Master 2 students with an analog/digital design profile.

Description

Are you eager to explore the backstage of microelectronics and learn how to turn a circuit design into a chip ready for fabrication? This internship invites you to take on an exciting challenge: setting up and running a complete open source design flow on related process technology, using an existing SAR ADC design as a motivating example.

The core mission is not to redesign the ADC, but to master the flow that makes such a design possible: installing the tools, configuring the PDKs, and validating each step of the process. How do you configure and launch open source EDA tools? How do you run simulations, placement and routing, and physical verification checks? What are the strengths and limitations of open source technologies in microelectronics design IC? You will be encouraged to explore these questions and propose your own answers.

• Starting date: Spring 2026
• Duration: 5-6 months
• Location: Grenoble, France

Your main tasks will include:

• Installing and configuring the open source design environment (PDK, EDA tools, automation scripts).
• Running the design flow on an existing SAR ADC as a case study.
• Carrying out simulation, synthesis, place-and-route, and DRC/LVS verification.
• Identifying bottlenecks and documenting reproducible solutions.

The student will be supported by an experienced team, with close mentoring and external collaborations to enrich your learning. He won't be left alone with the complexity of the flow – he will be guided, encouraged to test, and empowered to take initiatives. Indicative time allocation: ~30% installation and flow automation, 30% simulation and verification, 30% design adaptation, 10% analysis and scientific dissemination.

Candidate Profile

You are a master's student in microelectronics, embedded systems, or related fields. You have basic knowledge in digital/analog design, simulation, or VLSI concepts. You have basic experience writing scripts in bash/csh and are comfortable working in a Linux environment.

Supervisors: 

Youcef Fellah & Guillaume Regis

To apply, please contact: <youcef.fellah@cea.fr>

[mos-ak] [C4P] ICMTS 2026 Mar. 23-26, 2026 in Matsue, Japan

IEEE International Conference on Microelectronic Test Structures

Mar. 23-26, 2026 at Kunibiki-Messe Convention Center in Matsue, Japan

ICMTS 2026 Call for Papers

Abstract submission deadline: Nov 15, 2025

Looking for the best opportunity to present and discuss your ideas and results about test structures, measurements, and characterization? This is your chance! Join the 38th ICMTS conference.

This conference is co-sponsored by the IEEE Electron Devices Society. All presented papers will be submitted for potential inclusion in IEEE Xplore®. Original papers presenting new developments in topics relevant to ICMTS, include but not limited to test structures, measurements, and results, as outlined below. This one-track technical program will award a Best Paper that will be voted on by the Technical Program Committee. In addition, Tutorial Short Course will precede the main conference while several of the best measurement, equipment design, and manufacturing experts, will participate in the equipment exhibition and presentations.

• Design
• Methodologies, Verification
• Within-die circuits for process characterisation/monitoring
• Design enablement, characterisation and validation of digital and analog libraries
• Devices and Circuit Modelling
• Measurement techniques
• DC, AC and RF measurements: setup, test and analysis
• Reliability test - including thermal stability, failure analysis etc.
• Statistical analysis, variability, throughput increase, smart test strategies
• Use of machine learning and AI in analysis of data sets - parameter extraction etc.
• Wafer probing, within-die measurements, in-line metrology
• Throughput, testing strategies, yield enhancement and process control tests
• Applications
• Emerging memory technologies (single cell, arrays, and application in neural networks)
• Emerging transistor technologies for digital/analog/power applications
• Photonic devices - silicon integration, new displays (OLED, μ-displays)
• Flexible electronics and sensors (organic and inorganic materials)
• M(N)EMS, actuators, sensors, PV cells and other emerging devices

The author's abstract submission consists of up to four pages in PDF format (font-embedded). The first page should include a title, a 50-word summary, author name(s), full address, contact number and e-mail of the lead author, and any preference for oral or poster session presentation. The body of the abstract should consist of one page of text (800 to 1000 words) and up to two pages of major figures and tables.

The selection process will be based on the technical merit and will be highly weighted in favour of abstracts with high test structure content, giving a clear illustration of the test structure and including measurements and data analysis.

Abstract submission deadline: Nov 15, 2025

Notice of paper acceptance will be sent to the selected authors by Jan 17, 2026, with instructions for the expanded manuscript preparation for the conference proceedings. The deadline for submission of the final, camera-ready paper will be Feb 17, 2026.

Please join the ICMTS group at 

https://www.linkedin.com/groups/3804498    

if you have interest in all things, test and measurement.

Details of the venue, hotel, conference registration, etc. are available here.

If you have any questions, please contact the Technical Program Chair:

• Tatsuya OHGURO, tatsuya.ooguro@toshiba.co.jp
• Kejun XIA, kejun.xia@gmail.com

[mos-ak] [Special Issue] 7th International Sino MOS-AK Workshop

Special Issue on the 7th International Sino MOS-AK Workshop

Jun Zhang, Wladek Grabinski, Yuehang Xu (editors)

Int JNM, 38: e70114.

First published: 07 September 2025

https://doi.org/10.1002/jnm.70114

1. College of Integrated Circuit Science and Engineering, Nanjing University, Jiangsu (CN)

2. MOS-AK and GMC Consulting (CH)

3. School of Electronic Science and Engineering, Uni. Chengdu, Sichuan (CN)

As device structures become increasingly complex, with the continuous emergence of novel materials, unconventional architectures, and new physical phenomena, the coupling of multiple physical domains, including thermal, electrical, and optical effects, is becoming ever more prevalent. At the same time, rising development and manufacturing costs place additional demands on modelers to deliver representations that are both accurate and computationally efficient across the entire chain from device physics to circuit behavior. Modeling serves two complementary purposes: Theoretical models provide insight into the operating principles of devices, while also guiding design optimization and enabling engineers to fully exploit intertwined physical effects. Analytical modeling, however, often requires careful trade-offs among accuracy, generality, and simplicity. Models must be predictive enough to inform design while offering meaningful physical insight. In modern semiconductor devices, which often feature three-dimensional geometries, solving the coupled semiconductor physics equations analytically is extremely challenging or even impossible. Closed-form solutions are typically unattainable, so judicious simplifications are necessary to ensure that models remain tractable and practically useful.

The papers in this Special Issue address these challenges by balancing physical fidelity with computational efficiency. They deepen our understanding of device physics while providing models that are both insightful and practical, with applications spanning cryogenic electronics, wide-bandgap devices, and radiation-hardened systems.

Su et al. present a charge-based analytical model for bulk MOSFETs, that is, valid down to 10 mK. Their work clarifies the interface-trap-dominated mechanisms that lead to threshold voltage divergence between NMOS and PMOS devices and quantifies significant analog parameter enhancements, including a 73% increase in PMOS cutoff frequency at 4 K. These findings are essential for quantum-control electronics. Complementing this, Mao et al. provide a comprehensive review of four physics-based compact models for GaN HEMTs, namely MVSG, ASM HEMT, EPFL, and QPZD. They analyze how each model addresses challenges such as trapping effects, self-heating, and process variability, and highlight emerging opportunities for combining physical models with machine learning to accelerate parameter extraction and quantify uncertainties. In the area of radiation-tolerant electronics, Xu et al. introduce a machine-learning approach using an ant-colony-optimized neural network. By adaptively sampling critical waveform regions, their method achieves an RMS error of only 0.82% in predicting single-event transient currents, surpassing the fidelity limits of traditional double-exponential pulse models and enabling high-precision radiation effect simulation for aerospace applications. Meanwhile, Deng et al. demonstrate a practical strategy for AI-assisted SPICE integration. They employ geometry-parameterized scaling laws for spiral inductors and machine-augmented Power MOS trans-conductance models to accelerate parameter extraction by an order of magnitude while preserving full SPICE compatibility. This approach significantly streamlines industrial design workflows.

Collectively, these contributions point to a trend toward physics-informed, data-driven co-design methodologies. By combining rigorous physical insight with computationally efficient, machine learning–aware workflows, they enable robust optimization of devices and circuits across a wide range of applications, from quantum interfaces to aerospace systems.

Future research should prioritize the development of standardized interfaces between AI tools and physical models, the extension of models to three-dimensional integrated wide-bandgap architectures, and the establishment of co-design frameworks for emerging ultra wide–bandgap materials capable of operating in environments ranging from near-zero Kelvin to orbital radiation conditions. We sincerely thank all authors for their outstanding contributions, which have advanced the frontier of semiconductor modeling science.

[Read more...]

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[Deadline] extended to Oct.15 2026

10th IEEE Electron Devices Technology and Manufacturing

(EDTM 2026) Conference

https://ieee-edtm.org/

March 1-4, 2026 Penang, Malaysia 

EDTM2026 paper submission date has been extended to 15th October 2025

Submit your papers today in any of the 13 tracks and see you in Penang, Malaysia from 1st - 4th March 2026.

• Contributed papers will be judged for the best paper award for each technical track
• Each track will have Invited Speakers. Meet prominent Plenary and Keynote Speakers from Industry and academia for research, networking, innovation and commercialization purposes
• Exhibition and sponsorship opportunities to showcase breakthrough technology
• Extended versions of accepted papers to be published in 
• EEE Transactions on Materials for Electron Devices (T-MAT) and 
• Journal of IEEE Electron Devices Society (JEDS)

[workshop] Advances in Semiconductor and Emerging Devices for Chip Design

5-Day Online International Workshop on

Recent Advances in Semiconductor and Emerging Devices for Chip Design

Oct. 6-10, 2025

Organized by the Department of Electronics, Dhanamanjuri University (DMU), Manipur,

in Collaboration with IEEE Silchar Subsection

Upcoming 5-Day International Workshop on “Recent Advances in Semiconductor and Emerging Devices for Chip Design” (6–10 October 2025) organized by Dhanamanjuri University (DMU) Manipur, in collaboration with IEEE Silchar Section. This unique event, led by Dr. Khoirom Johnson Singh, Ph.D. and his dedicated team, brings together global experts from India, Europe, and beyond. Register Online

With speakers covering topics from GaN devices and memristors to cryogenic CMOS, nanosheet FETs, biomedical circuits, and spintronics for novel computing, this workshop will serve as a melting pot of ideas, a platform for young researchers and students to learn, question, and seed new collaborations.

Education equips young minds with the foundations of knowledge, preparing them to understand technological advancements and their role in shaping society. Yet, in research, knowledge alone is not enough. To truly innovate, we must disseminate our work, engage with peers, and foster collaborations across disciplines and borders. This is where the seeds of research truly take root and grow.

Collaboration is more than sharing data or co-authoring papers. It is about bringing together diverse perspectives, connecting physics with engineering, theory with experimentation, and academia with industry. Interdisciplinary approaches not only accelerate breakthroughs, but also open new directions that no single researcher could achieve alone.

Register Online...

[paper] Is there anything left to do in TCAD?

Z. Stanojevic, F. Schanovsky, G. Rzepa, X. Klemenschits, H. Demel, 

O. Baumgartner, C. Kernstock, and M. Karner

Is there anything left to do in TCAD?

SISPAD  in Grenoble, Sept. 24 2025

https://sispad2025.inviteo.fr/

1. Global TCAD Solutions GmbH., Bosendorferstraße 1/12, 1010 Vienna (A) 

Abstract: Over the past decade, the development of commercial technology computer-aided design (TCAD) software has followed an evolutionary rather than revolutionary path. Alongside established continuum and particle-based approaches in both process and device simulation, advanced carrier transport models - such as deterministic bulk and subband Boltzmann transport equation (BTE) solvers and non-equilibrium Green’s functions (NEGF) - have been incorporated into the TCAD toolkit for single-device simulation. At the system level, the field of design-technology co-optimization (DTCO) has expanded to encompass variability, reliability, and the extension of TCAD methodologies from devices to circuits. However, most of these innovations were introduced over a decade ago, prompting the question: What remains to be developed in TCAD? We address this question by analyzing current limitations and potential future directions in TCAD development across three key dimensions: (1) fidelity, (2) integration, and (3) efficiency - each with particular relevance in commercial and industrial contexts. We examine ongoing challenges in classical TCAD, advanced transport modeling, and DTCO flows, and point to potential directions for future developments. Among these, we include various methodologies related to machine learning and hardware accelerators, particularly within the efficiency dimension.

FIG: Device 3D structure generated from a layout (GDSII) and a technology file

See also...

[paper] THz MOST based on aligned carbon nanotube arrays

Jianshuo Zhou, Zipeng Pan, Li Ding, Lin Xu, Xiaohan Cheng, Haitao Li, Fenfa Yao, Chuanhong Jin, Maguang Zhu, Lijun Liu, Huiwen Shi, Zhiyong Zhang and Lian-Mao Peng

Terahertz metal–oxide–semiconductor transistors based on aligned carbon nanotube arrays. 

Nat Electron (2025)

DOI: https://doi.org/10.1038/s41928-025-01463-6

1. Key Laboratory for the Physics and Chemistry of Nanodevices and Center for Carbon-based Electronics, Peking University
2. Hunan Institute of Advanced Sensing and Information Technology, Xiangtan University, Xiangtan, China
3. Chongqing Institute of Carbon-based Integrated Circuits, Peking University, Chongqing, China
4. Academy for Advanced Interdisciplinary Studies, Peking University, Beijing, China
5. State Key Laboratory of Silicon and Advanced Semiconductor Materials, Zhejiang University, Hangzhou, China
6. Frontiers Science Center for Nano-optoelectronics, Peking University, Beijing, China

Abstract: Films of aligned semiconducting carbon nanotubes could be used to build complementary metal–oxide–semiconductor field-effect transistors for digital integrated circuits and radio-frequency transistors for terahertz analogue integrated circuits. However, the operating frequencies of such devices remains too low for potential application in the sixth generation of wireless communications. Here we report metal–oxide–semiconductor field-effect transistors that are based on aligned carbon nanotube films and have a cut-off frequency beyond 1 THz. By optimizing gate structures and fabrication processes, we create devices with a gate length of 80 nm that have a carrier mobility of over 3,000 cm2 V−1 s−1, as well as an on-state current of 3.02 mA µm−1, a peak transconductance of 1.71 mS μm−1 at a bias of −1 V, and a saturation velocity of 3.5 × 107 cm s−1. By introducing a Y-shaped gate, we also create devices with gate lengths of 35 nm that have an extrinsic cut-off frequency (fT) of up to 551 GHz and a maximum oscillation frequency (fmax) of 1,024 GHz. Finally, we use devices with a gate length of 50 nm to fabricate mmWave-band (30 GHz) radio-frequency amplifiers that have a gain of up to 21.4 dB.

Fig: Characteristics of Y-gate structure in A-CNT MOSFETs.

Acknowledgements: This work is supported by the National Key Research & Development Program (grant number 2022YFB4401603 to L.D.) and Natural Science Foundation of China (grant numbers 62171004 to L.D., 92477201 to L.-M.P. and 62225101 to Z.Z.).

[Thesis] Verilog-A MOSFET Model for Analog IC Design

Verilog-A Based Implementation of a MOSFET Model for Analog Integrated Circuit Design

Master Thesis by Alba Gallego Velázquez

Defended: July 1, 2025

Technical University of Crete, Chania

Tutor: Prof. Matthias Bucher

Abstract: The present thesis sets out the development and implementation of a compact model of a MOSFET, based on the theoretical EKV model, and implemented using the Verilog-A language. The utilization of simulation and compilation environments, such as the open server OpenVAF and Ngspice, is instrumental in facilitating the effective execution of the work. The construction of a model that can perform the function of an nMOS or a pMOS nanometric operating in a saturated state is facilitated by these. In this model, physical dependencies and second-order effects are incorporated, ensuring the attainment of continuous expressions for all inversion regions. The model's behavior is validated against experimental data by means of simulation. This results in an accurate, compact and versatile model, which is suitable for supporting integrated analog circuits designs with a wide range of values for the inversion coefficient.

Fig: Normalized (𝐺𝑚𝑠 ·𝑈𝑡)/ID of the nMOS vs. the inversion coefficient (IC)

[paper] Gate stack engineering of 2D transistors

Yeon Ho Kim, Donghun Lee, Woong Huh, Jaeho Lee, Donghyun Lee, 

Gunuk Wang, Jaehyun Park, Daewon Ha and Chul-Ho Lee*

Gate stack engineering of two-dimensional transistors.

Nat Electron 8, 770–783 (2025)

DOI: 10.1038/s41928-025-01448-5

* Laboratory of Emerging Electronics & optoElectronics, SNU / julianus95@snu.ac.kr

Abstract: Gate stack engineering has helped enable aggressive device scaling in silicon complementary metal–oxide–semiconductor technology. Two-dimensional (2D) materials are a potential replacement for silicon in next-generation electronics. However, creating gate stacks that are capable of effective and reliable channel control with such materials is inherently challenging owing to the lack of compatible dielectrics and fabrication methods. Here we explore the development of gate stack engineering technologies for two-dimensional transistors. We benchmark key performance metrics for two-dimensional metal–oxide–semiconductor gate stacks against current silicon-based technologies, as well as the targets set by the International Roadmap for Devices and Systems. We also highlight recent advances in ferroelectric-embedded gate stacks, which offer additional functionalities and could be of use in the development of high-speed non-volatile memories and logic-in-memory devices, as well as low-power transistors. Finally, we consider the technical challenges that need to be addressed to develop advanced electronic technologies based on two-dimensional transistors.

FIG: CMOS logic technology roadmap and potential of angstrom-scale 2D transistors

Acknowledgment: This research was supported by the Ministry of Science and ICT under the Next-Generation Intelligent Semiconductor Technology Development Project and the Nano and Material Technology Development Program (Future Technology Labs). The graduate researchers received additional support from BK21 Four and the SNU Graduate School of AI Semiconductor.

[Online Publications] 22nd MOS-AK/ESSERC Workshop in Munich (D) on Sept. 8 2025

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

MOS-AK/ESSERC Workshop

Munich, Sept.8, 2025

The consecutive, 22nd MOS-AK Workshop has been organized as an integral part of 51st ESSERC in Munich (D) on Sept. 8 2025. The MOS-AK workshop publications [1-6], with individually assigned DOI numbers, are available online at:

<https://www.mos-ak.org/munich_2025/>

The development of open-source Process Design Kits (PDKs) is crucial for democratizing access to advanced semiconductor technologies. IHP's OpenPDK initiative bridges the gap between academia, startups, and the semiconductor industry by offering a fully open and manufacturable SG13G2 BiCMOS OpenPDK for analog/RF, mixed-signal, and digital IC applications. Aligning with the EU Chips Act, this initiative emphasizes open collaboration to overcome economic and technical barriers in semiconductor innovation. The workshop introduces SG13G2 OpenPDK and Free and Open-Source Software (FOSS) tools for IC designs, including Verilog-A devices, schematic capture, SPICE simulation, layout, physical verification in advanced design flow up to final typeout.

To learn more about IHP OpenPDK Initiative and its Certified Design Courses, visit online depositories as listed below:

Open-Source Digital Design Course: https://github.com/OS-EDA/Course

• Full RTL-to-GDSII workflow using OpenROAD and SG13G2 PDK
• Feedback integrated via GitHub & live sessions
• Trial run Feb 2025: 15 on-site participants selected from 85+ applicants

Open-Source Analog Design Course: https://github.com/IHP-GmbH/IHP-AnalogAcademy

• Hands-on design with SG13G2 PDK; Strong emphasis on analog/RF practice, focused on the layout and verification, including process variation analysis of analog/RF ICs
• Explored designs: Bandgap, 50 GHz PA, SAR ADC
• Tools: Ngspice, Xyce, Xschem, Qucs, Klayout
• Trial run June 2025: with 16 on-site participants selected from 80+ applicants

MOS-AK Workshop References:

[1] M. Yazici and R. Scholz, "IHP OpenPDK Roadmap", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113282.

[2] Árpád Bűrmen, "The OpenVAF Verilog-A Compilerfor the OpenPDK Ecosystem", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113774.

[3] M. Volker, "User-friendly FDTD EM Workflow for IHP OpenPDK with Automatic Meshing", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113926.

[4] Mike Brinson, "Building Component Libraries for Use with the IHP OpenPDK and FOSS Tools", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113932.

[5] Mirjana Videnović-Mišić, "Analog IC Flow Automatization", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113935.

[6] Ralph Steiner Vanha, "MOS SizingTool – A Single Transistor Simulator", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113946.

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[paper] MicroLEDs SPICE Model

Sultan El Badaoui1,2, Patrick Le Maitre1, Anthony Cibié1, Julia Simon1, Aurélien Lardeau-Falcy1, 

Jeremy Bilde1, Louwenn Cherruault1, Manon Arch1, Michael Pelissier1, Yannis Le Guennec2

SPICE Modeling of GaN MicroLEDs for Optical Communication

Journal of the Society for Information Display, 2025; 0:1–16

DOI 10.1002/jsid.2105

1 Univ. Grenoble Alpes, CEA LETI, Minatec, Grenoble (F)
2 Univ. Grenoble Alpes, CNRS, Grenoble-INP, GIPSA-lab, Grenoble (F)

Abstract: With the rapid expansion of data centers, there is a growing demand for high data-rate, energy-efficient optical links over short distances. One potential technology for this application is Gallium-Nitride (GaN) based microlight emitting diodes (μLEDs), thanks to their compact size, high-speed operation, and ease of manufacturability. During the development of these μLEDs, modeling plays an essential role in optimizing their performance. In this paper, we present various models to estimate both the static and dynamic performance of GaN μLEDs of various sizes. We then propose a methodology to integrate these models into a unified equivalent circuit model, enabling the simulation of the full response of the μLED. Finally, we implement this unified model in a circuit-simulation-compatible module and replicate the experimental setups within a simulation software to evaluate the module's ability to accurately simulate the μLED's response.

FIG: (a) SEM image of a 50-μm μLED, showing the GSG pad configuration and the grid contact over the μLED

(b) Schematic of the stack of the μLEDs 

9c) Simulation setup used to for transient simulation

Acknowledgments: This work is part of the IPCEI Microelectronics and Connectivity and was supported by the French Public Authorities within the frame of France 2030 and by the Institut Carnot CEA-Leti.

[Conference] 33rd Austrochip 2025

Austrochip 2025

33rd Austrian Workshop on Microelectronics

September 25, 2025 – Linz, Austria

The TT workshop program

Conference Program

08:00 – 09:00 Coffee & Registration
09:00 – 09:15 Conference Opening
09:15 – 10:00 First Keynote-Address

• IHP OpenPDK and MPW: Pushing Open-Source EDA tools to Analog and RF Design René Scholz IHP – Leibniz Institute for high performance Microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany

10:00 – 10:45 Second Keynote-Address

• Open-source SoC design using PULP Frank K. Gürkaynak ETH Zürich, IIS, ETZ J 60.1, Gloriastrasse 35, 8092 Zürich, Switzerland

10:45 – 11:00 Break
11:00 – 12:00 Paper Session I:
Session Chair: TBA, TBA

• Gain Expansion Generator based on a Reduced Conduction Angle for H-Band Applications Thomas Ufschlag, Benjamin Schoch, Lukas Gebert, Dominik Wrana, Axel Tessmann and Ingmar Kallfass University of Stuttgart (ILH), Fraunhofer Institute for Applied Solid State Physics IAF
• Greyhound: A Reconfigurable and Extensible RISC-V SoC and eFPGA on IHP SG13G2 Leo Moser, Meinhard Kissich, Tobias Scheipel and Marcel Baunach Graz University of Technology
• Comparison of Low Power Digitally Controlled Ring Oscillator Architectures in 12 nm FinFET Florian Schneider, Luca Avallone and Alicja Michalowska-Forsyth Infineon Technologies Austria AG Institute of Electronics (IFE), Graz University of Technology

12:00 – 12:30 Poster & Sponsor Pitch Session
12:30 – 14:00 Lunch
14:00 – 15:15 Paper Session II:
Session Chair: TBA, TBA

• A 150-GHz 9-dBm EIRP Open-Source FMCW Radar Chip in 130-nm BiCMOS Ghaith Al Sabagh, Georg Zachl and Harald Pretl Institute for Integrated Circuits and Quantum Computing, JKU Linz

• A CMOS Source-Coupled Relaxation Oscillator Achieving Close-in Phase Noise of −72.9 dBc/Hz at a 1 kHz Offset Baset Mesgari, Saeed Saeedi, Reinhard Feger and Horst Zimmermann Institute for Communications Engineering and RF-Systems, Johannes Kepler University Linz Faculty of Electrical and Computer Engineering, Tarbiat Modares University Christian Doppler Laboratory MWTH

• A FR3, 25 dBm Unbalanced MMIC GaAs Doherty Power Amplifier with Auxiliary Gate Voltage Modulation for Linearity Improvement Abdolhamid Noori, Fatemeh Abbassi, Christoph Wagner, Christian Fager and Gregor Lasser Chalmers University of Technology, Silicon Austria Labs

• A 72.7-90.4 GHz VCO with a Stacked NMOS based Tuning Network in 28nm FDSOI Waseem Abbas, Samir Aziri and Christoph Wagner Silicon Austria Labs

• A D-Band Active Down-Conversion Mixer with 80 GHz IF for FMCW Radar Frequency Extension Fatemeh Abbassi, Samir Aziri, Waseem Abbas, Christoph Wagner and Timm Ostermann Silicon Austria Labs, Institute for Integrated Circuits and Quantum Computing, JKU Linz

15:15 – 15:30 Break
15:30 – 16:45 Paper Session III:
Session Chair: TBA, TBA

• Design Automation of a Digitally Controlled Ring Oscillator using CUAS Cell Creator Framework Daniel Cerdà Holmager, Santiago Martin Sondón, Violeta Petrescu, Wolfgang Scherr and Johannes Sturm Carinthia University of Applied Sciences in Austria, CUAS
• Event-Based ADCs vs. Nyquist ADCs: Rethinking Performance Metrics Simon Dorrer, Anna Werzi, Bernhard A. Moser, Michael Lunglmayr and Harald Pretl Institute for Integrated Circuits and Quantum Computing, JKU Linz Institute of Signal Processing, JKU Linz
• Modeling Location-dependent Random Telegraph Noise for Circuit Simulators Florian Berger, Gerhard Landauer, Alicja Michalowska-Forsyth, Martin Flatscher, Philipp Greiner and Stefan Gansinger Institute for Electronics, Graz University of Technology Power and Sensor Systems, Infineon Technologies
• An 8.1-µW 12-bit Non-Binary Self-Clocked SAR-ADC in 130 nm Open-Source PDK Ali Olyanasab, Patrick Fath, Leonhard Schreiner, Christoph Guger and Harald Pretl g.tec medical engineering GmbH Institute for Integrated Circuits and Quantum Computing, JKU Linz
• SPAD Active Quenching/Resetting Circuit in 0.35-µm HV-CMOS Enabling 24V Excess Bias for PDP >90% Sherwin Nasirifar, Baset Mesgari, Christoph Ribisch, Saman Kohneh Poushi and Horst Zimmermann Institute of Electrodynamics, Microwave and Circuit Engineering, TU Wien Institute for Communications Engineering and RF Systems, JKU Linz Austrian Institute of Technology (AIT), Vienna Silicon Austria Labs

16:45 – 17:00 Conference Closing, Best Paper Award & Outlook Austrochip 2026

Aging Model for ASAP 7nm Predictive PDK

Neha Gupta¹, Lomash Chandra Acharya¹, Mahipal Dargupally¹, Khoirom Johnson Singh², Amit Kumar Behera¹, Johan Euphrosine³, Sudeb Dasgupta¹, Anand Bulusu¹

Aging Model Development for ASAP 7 nm Predictive PDK: Application in Aging-Aware Performance Prediction of Digital Logic and ADCs in Data Acquisition System

IEEE ISVLSI (2025)

DOI: 10.1109/ISVLSI65124.2025.11130265

1 Indian Institute of Technology, Roorkee, (IN)
2 Dhanamanjuri University, Manipur (IN)
3 Google, Tokyo (J)

Abstract: As semiconductor technology advances to sub- 10nm nodes, Design Technology Co-Optimization (DTCO) has emerged as an essential paradigm for co-optimizing processes and design methodologies. Although the ASAP 7nm Predictive PDK (Process Design Kit), which is a free and open-source academic PDK developed by the Arizona State University (ASU) research team, is a useful open-source platform for digital design research, it lacks key DTCO features such as reliability modeling, aging resilience, and security-aware co-design. In this article, we present our developed aging model for ASAP 7nm Predictive PDK and utilize it to evaluate the impact of transistor aging on the performance of digital timing logic and a memory cell which provides timing feedback from a DTCO point-of-view concerning standard cells and other reference circuit designing. In this work, different logic gates, benchmark circuits, N-stage ring oscillator and 6T SRAM bitcell are used as the representative of digital logic and memory cell, respectively. We further utilize our developed aging model to predict performance of an analog-to-digital converter in data acquisition systems. The developed aging model would be released for the research community for further improvement in design reliability and technology enhancement along with OPENROAD Tool flow.

Fig. (a) Flow chart for representing steps required to develop Verilog-A aging model 

for ASAP 7nm Predictive PDK (FinFET) process. 

(b) Inclusion of the developed aging model to incorporate aging impact in static timing analysis (STA).