Jul 24, 2025

[rsvNumerics] hands-on transistor sizing for analog ICs

rsvNumerics – info@rsvn.ch
Copyright © 2025 rsvNumerics – All Rights Reserved

rsvNumerics provides concepts, guidance and software tools for sizing transistors in integrated circuits with an easy-to-learn methodology. Whether you are a novice or an expert, you can benefit from our methodology and dimension your devices in no time, serving as a near-perfect starting point for your verification. Moreover, our methodology is not limited to a few predefined circuit topologies; it works for literally any circuit in any application.

rsvNumerics in Circuit Design General, SizingTool



The schematic of the constant-𝑔𝑚 bias circuit is shown above. It consists of two cross-coupled current mirrors, where one of the source contacts, e.g. of an NMOS transistor, is degenerated by a source resistor. This results in a unique operating point of the circuit other than zero current, which defines the pass current in the two branches.

The corresponding settings of SizingTool 3 for transistor 𝑁𝑀0 and for transistor 𝑁𝑀1 are given in Fig above. Once the drain currents for a constant-𝑔𝑚 biasing block are known, we can use the information when designing any other transistor with derived source current. However, there its drain current has to be readjusted each time the process corner is changed to reflect for constant-𝑔𝑚 biasing, which is tedious, and is addressed by the current weighing option.

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[paper] Gradient Minimization in Layout Patterns for Analog Circuits

Isaac Bruce, Michael Sekyere, Ruohan Yang, Saeid Karimpour, Colin C. McAndrew, Degang Chen
Gradient Minimization in Layout Patterns for Analog Circuits
Circuits, Systems, and Signal Processing. 1-22.
DOI: 10.1007/s00034-025-03158-x

1 Department of Electrical and Computer Engineering, Iowa State University, Ames, IA, USA
 
Abstract: In this paper, we present an algorithm to generate the layout of a pair of devices A and B for a given matching ratio r and total unit cell count N that minimizes the mismatch due to systematic gradient effects. The algorithm relies on simple reflections and rotations of an initial optimized pattern across 4 quadrants. The approach cancels all odd-order systematic gradients and minimizes 2nd order systematic gradients. The method can easily be extended to cancel higher-order even gradient effects. The validity of the proposed algorithm is demonstrated via numerical simulations. Additionally, an electrothermal simulation of a set of layouts is run to further validate the proposed layout generation scheme.

FIG: Layout of circuit design with heat sources and current sources 
for the optimal transistor array pattern.

Jul 16, 2025

[mos-ak] 一生一芯 2025 Summer Launch Conference


 One Student, One Chip
2025 Summer Launch Conference


🗓 Conference Details

  • Date & Time: July 21st (Monday), 14:30
  • Location: Room 104, Mingde Campus, Shenzhen University, Nanshan District, Shenzhen, Guangdong Province
  • Participation: Online registration open until July 19th, 23:59
  • Live Stream: Bilibili Live Broadcast Link

🎓 About the Project

The "One Student One Chip" (一生一芯, ysyx.org) program is an open-source, free, and public training platform aimed at developing full-stack engineers proficient in both hardware and software. It's designed for lifelong learners of all ages—from primary school to university—without limitations. Students are guided in designing and implementing a RISC-V CPU, using:

  • Chisel (hardware description language)
  • FPGA tools
  • DK development environment

They explore concepts spanning:

  • Digital logic
  • RTL design
  • Computer architecture
  • Operating systems
  • Compilers

Since its 2019 launch, the program has involved over 12,000 students, with backing from top universities including Tsinghua, Peking, and Fudan.


🌟 Key Highlights for 2025

  1. New teaching materials with a hierarchical learning model (EDCBA) to enhance learning efficiency
  2. Post-course chip design program with ECOS Studio tools and open-source test platforms
  3. Launch of MOLI Learning Platform, offering curated courses from universities like MIT, Tsinghua, and Peking University

🏫 Supporting Institutions

  • Tsinghua University
  • Peking University
  • Fudan University
  • Zhejiang University
  • Shanghai Jiao Tong University
  • University of Science and Technology of China
  • Harbin Institute of Technology
  • National University of Defense Technology


Jul 15, 2025

[mos-ak] [Media Note] MOS-AK Workshop, London, July 11, 2025

MOS-AK Workshop 2025 Held at London Metropolitan University [MOS-AK Media Note]

The MOS-AK Compact Modelling Workshop was successfully hosted on July 11, 2025, at London Metropolitan University, bringing together a diverse group of researchers, engineers, and industry professionals to explore recent advances in compact modelling, semiconductor technologies, and circuit simulation. This in-person event marked a valuable opportunity for participants to reconnect face-to-face, exchange ideas, and foster collaboration across institutions and disciplines.

The workshop featured a distinguished panel of presenters from academia, research institutions, and industry. These experts delivered high-quality technical talks covering a broad range of cutting-edge topics in compact device modelling, circuit design, and emerging applications. The presentations covered innovative research and development in the following areas:
  • Open PDK Progress: "IHP-Open-PDK Review: Present Status and Future Directions" Dr. Krzysztof Herman -  IHP Leibniz Institute for High Performance Microelectronics

  • Open PDK Progress: "The Application of FOSS Tools in the Design of IHP Open-Access 130nm BiCMOS RF Integrated Circuits" Prof. Mike Brinson -  London Metropolitan University

  • Open PDK Progress: "Presentation and Evaluation of the 1st IHP Open Source Analog Certificate Course" Phillip Ferreira Baade-Pedersen -  IHP Leibniz Institute for High Performance Microelectronics

  • Biomedical Sensing: "Non-invasive Biomedical Sensor for Dehydration Monitoring" Prof. Bal Virdee and Innocent Lubangakene London Metropolitan University (UK)

  • Quantum Modelling: "Compact Quantum Dot Models for Analog Microwave Co-Simulation"
    Lorenzo Peri -  Quantum Motion and University of Cambridge

  • Cryogenic Electronics: "Deep-Cryogenic Device Characterisation in a CMOS Foundry Process"
    Grayson Noah -  Quantum Motion

  • Compact Modelling: "Developments of Compact Models for Source-Gated Devices"
    Dr. Patryk Golec -  École Polytechnique, Paris

  • Display and Bio Circuits: "Area- and Energy-Efficient Current-Mode Pixel Circuits for High-Performance Display and Life Science Applications"
    Dr. Eva Bestelink -  University of Surrey

  • Novel Transistor Behaviour: "Opportunities for Modelling Off-State Behaviour in Polysilicon Contact-Controlled Transistors"
    Prof. Radu A. Sporea -  University of Surrey


Each session stimulated thoughtful discussion and knowledge sharing among attendees, reinforcing the relevance of compact modelling in enabling innovation across semiconductor technologies.

The event was organized by London Metropolitan University with the support of the Institution of Engineering and Technology (IET) and the IEEE Electron Devices Society, and was generously sponsored by the IHP Leibniz Institute for High Performance Microelectronics.
A total of 35 delegates attended the workshop, representing a mix of academia, research labs, and industry. The workshop concluded with a networking drinks reception, providing attendees a relaxed environment to engage in informal discussions, build professional connections, and explore collaborative opportunities.

-- Prof. Bal Virdee, Prof. Mike Brinson and W.Grabinski for Extended MOS-AK Committee
WG150725

Jul 14, 2025

[mos-ak] [Final Program] 22nd MOS-AK/ESSERC Workshop in Munich (D) Sept. 8, 2025

Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
MOS-AK/ESSERC Workshop in Munich
September 8, 2025

Scheduled consecutive 22nd MOS-AK/ESSERC SPICE/Compact Modeling T2 Workshop organized in Munich, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and FOSS CAD/EDA tool developers and vendors. The content will be beneficial for anyone who needs to learn what is really behind the FOSS CAD/EDA IC simulation in modern device models in OpenPDKs. The MOS-AK workshop program is available online

It will be followed by ESSERC T2 Tutorial "Design and Simulation of Analog/RF Integrated Circuits with Open-Source CAD Tools and Process Design Kits". T2 tutorial explores how FOSS CAD/EDA tools and OpenPDKs empower IC designers. T2 also introduces ACM2, a compact, physics-based MOSFET model, with hands-on guidance on design parameter extraction for analog/RF circuit applications using the IHP OpenPDK 130nm BiCMOS process.

Online Registration is open (Early: until Friday July 18, 2025 (23:59 CEST))
any related enquiries can be sent to registration@mos-ak.org

-- W.Grabinski on the behalf of International MOS-AK TPC Committee

Enabling Compact Modeling R&D Exchange

WG140725

Jul 9, 2025

[mos-ak] [C4P] Austrochip 2025

Call for Papers – Austrochip 2025
Submission Deadline: July 24, 2025

We, JKU, Local Organizer and Host, are excited to invite submissions for Austrochip 2025 – The 33rd Austrian Workshop on Microelectronics, happening on September 24-25, 2025, in Linz, Austria. This workshop is a key platform for sharing advancements in microelectronics, connecting researchers, and fostering collaboration. If you're working on innovative designs, methodologies, or applications, we'd love to see your work!

For submission details and guidelines, visit: https://iic.jku.at/austrochip/pages/call-for-papers.html

Join us for an exciting workshop and conference on the future of microelectronics!


Jul 1, 2025

[mos-ak] [OpenPDK] IHP Analog Academy

IHP Analog Academy


We, IHP Analog Academy, are excited to present this deep dive into analog, RF, and mixed-signal IC design, powered by open-source FOSS CAD/EDA tools and the IHP Open PDK.

This hands-on course is designed for engineers, researchers, and students eager to gain practical experience with the SG13G2 process at the 130nm technology node. Originally hosted on-site at IHP in Frankfurt (Oder), participants spent five intensive days exploring everything from fundamental analog simulation to advanced RF, 3D EM modeling, and mixed-signal integration. And now we're excited to release it to the open-source community!

The course covers:
- Bandgap reference design and simulation using the gm/Id methodology
- RF design of a 50 GHz Medium Power Amplifier with EM simulation
- Mixed-signal integration and verification of an 8-bit SAR ADC

Each module emphasizes a real-world design flow using tools like:
ngspice, Xyce, KLayout, OpenEMS, QUCS, and Python for data analysis.

Over time, we will expand the repository with:
- More modules
- Updated toolchain support
- Improvements to existing flows

Explore the IHP Open PDK:
- Open PDK GitHub Repository https://github.com/IHP-GmbH/IHP-Open-PDK 
- Interactive Help via ChatGPT https://chat.openai.com

Note: This is not an introductory IC design course. A basic understanding of electronics and microelectronics is assumed. We're proud to contribute this initiative to the community to help lower the barrier to IC design using open-source tools. We encourage contributions via GitHub Issues or Pull Requests! Your feedback and contributions, are welcome!

Lead Author: Phillip Ferreira Baade-Pedersen
Co-Author: Christian Wittke

The Development of this course is funded by the public German project FMD-QNC (16ME083) from BMFTR (Federal Ministry of Research, Technology and Space / Bundesministerium für Forschung, Technologie und Raumfahrt): https://www.elektronikforschung.de/projekte/fmd-qnc

#opensource #analog #mixedsignal #rf #design

Compact MOSFET Mechanical Stress Model

Bonev, Nikolay, Dirk Michael Nuernbergk, and Christian Lang
Inclusion of Mechanical Stress Effects in a Compact MOSFET Model
Science and Technology 28, no. 2 (2025): 138-149.
DOI: 10.59277/ROMJIST.2025.2.02

1 Melexis Bulgaria EOOD, Sofia, Bulgaria
2 Melexis GmbH Erfurt, Erfurt, Germany

Abstract: The analog performance of integrated circuits relies on stable parameters of its transistors. Mechanical stress changes the electronic properties of silicon and, therefore, also the device parameters. For circuit design, a good model of these effects is needed for a predictable and reliable function of the circuits. This article extracts the changes of various MOSFET parameters under effect of mechanical stress. A compact description of the stress effects is derived by applying tensors of piezo coefficients. The deviations are included in the physically based compact EKV model. A comparison with measured data shows that the stress effects are modelled correctly within a 10 % error margin.

Fig: Extraction setup for the specific current Is


Jun 21, 2025

Technical Lecture - the Celebration of FET100


You are all invited to register and attend the Technical Talks being organized by 
IEEE Electron Device Society (EDS) Delhi Chapter – India and IEEE EDS Community Engagement Ad-hoc Committee 
along with The National Academy of Sciences, India-Delhi Chapter; 
Science Foundation Committee of Deen Dayal Upadhyaya College, University of Delhi, New Delhi, INDIA

Kindly register for each talk separately and forward the email to your students and other colleagues.

Technical Lecture on June 23, 2025 @ 03:00 pm Italy time (GMT +2) i.e. 06:30 pm India Time (GMT +5.30)
The Field Effect Transistor - Evolution of the Modeling ApproachesMassimo Rudan, Professor EmeritusIEEE Life FellowDepartment DEI, University of BolognaSchool of Engineering, Bologna, Italy

Technical Lecture on June 25, 2025 @ 12:00 pm Aachen, North Rhine-Westphalia, Germany (GMT +2) i.e. 03:30 pm India Time (GMT +5.30).
A Brief History of Device Simulation for MOSFETsChristoph JungemannRWTH Aachen University

Technical Lecture on June 27, 2025 @ 02:00 pm (GMT+2) Time in Stockholm, Sweden i.e. 05:30 pm (GMT + 5:30) Indian Standard Time
Efficient Semiconductor Devices for a Sustainable FutureProfessor Mikael Östling, KTH Royal Institute of Technology, FIEEESchool of EECS, Stockholm, Sweden

Technical Lecture on June 30, 2025 @ 04:30 pm CET (GMT+2) Time in Madrid, Spain which shall be 08:00 pm Indian Standard Time (GMT +05:30)
History, evolution and perspective of Thin Film Transistor technologiesBenjamin IñiguezUniversitat Rovira i VirgiliTarragona, Spain

Technical Lecture on July 01, 2025 @ 09:00 am your time (GMT - 5) i.e. 07:30 PM Indian Standard Time (GMT +5:30)
Moore's Law and Radiation Effects on MicroelectronicsDaniel M FleetwoodOlin H. Landreth Professor of Engineering, Professor of Electrical and Computer Engineering, Professor of PhysicsVanderbilt University

Technical Lecture on July 01, 2025 @ 10:00 am (UTC - 5) i.e. 08:30 PM Indian Standard Time (GMT +5:30)
Perovskites – The New Frontier for Solar Photovoltaic Energy Conversion: Science and TechnologyVikram DalalFellow: IEEE, APS, AAASAnson Marston Distinguished ProfessorIowa State University, USA

Technical Lecture on 
July 2, 2025 @ 4:00 pm Italy time (GMT +2) i.e. 07:30 PM Indian Standard Time (GMT +5:30)
Nanoelectronics and Nanosystems Device Engineering for Sustainability, in the Energy and Variability Efficiency(E.V.E.) EraSimon Deleonibus, Life Fellow IEEE, Emeritus Fellow Electrochemical Society, Alternatives, Laboratoire d'Electronique et des Technologies de l'Information,(CEA-LETI), Grenoble, France.

Technical Lecture on
July 3, 2025 @ 10:30 am Italy time (GMT - 4) i.e. 08:00 PM Indian Standard Time (GMT +5:30)
Spin-field effect transistor – the unusual FETSupriyo Bandyopadhyay, Dept. of Electrical and Computer Engineering, Virginia Commonwealth University, Richmond, VA 23284

-- with regards -- Manoj Saxena

Professor Manoj Saxena | आचार्य मनोज  सक्सेना 
FNASc(IN), FIETE(IN), SMIEEE(USA)
Department of Electronics | इलेक्ट्रॉनिक्स विभाग
Deen Dayal Upadhyaya College | दीन दयाल उपाध्याय कॉलेज
University of Delhi | दिल्ली विश्वविद्यालय
Dwarka Sector-3, New Delhi-110078 | द्वारका क्षेत्र -, नई दिल्ली -११००७८
India | भारत

Jun 20, 2025

[C4P] Micro Nano & Chips Tech 2025

 
12th International Conference on Micro-Nano & Chips Tech

Dear Colleagues,

You are cordially invited to participate in 

MICRO NANO & CHIPS TECH 2025

the 12th edition of the International Conference on Micro-Nanoelectronics, Nanotechnology and MEMS. 

The event will take place at the Cultural Center of Chania in Crete, Greece, from November 6 to 9, 2025.

Paper submissions are now open!

For more information, please visit the conference website: https://2025.micro-nano.gr/ 


Jun 12, 2025

[mos-ak] [Media Note] MOS-AK INAOE Workshop, Puebla (MX)

MOS-AK INAOE Workshop on Semiconductor Technologies
Puebla (MX), May 14-16, 2025

Media Note

The MOS-AK Workshop on Semiconductor Technologies was held at the Instituto Nacional de Astrofísica, Óptica y Electrónica (INAOE) in Tonantzintla, Puebla, México, on May 14-16, 2025. This workshop was sponsored by MOS-AK, the INAOE, and IEEE through the Puebla Section and the local chapters for the Electron Devices and Instrumentation and Measurements societies. The MOS-AK event was inaugurated by Dr. Wladek Grabinski representing MOS-AK and IHP; Dr. David Sánchez, INAOE's General Director, Dr. Claudia Feregrino, Director of Research and Development for INAOE, and Dr. Roberto Murphy, the local organizer.

The objective of the workshop was to present the various open source tools for the design and simulation of integrated circuits (ICs). It consisted of in person as well as remote keynote speeches by experts in the field, and of a three-hour workshop on digital design synthesis.

The opening talk was by Dr. Wladek Grabinski (MOS-AK), covering a description of all the available FOSS CAD/EDA tools and programs for the design, simulation and fabrication of ICs using OpenPDK. This was a very enlightening run-through of the opportunities that can be exploited by all those who work in the field, at all levels. 

It was followed by a conference by Dr. Joaquín Faneca Ruedas, from the Centro Nacional de Microelectrónica (CNM) in Barcelona, Spain. He spoke about silicon nitride photonics, which is fast becoming a scalable platform for integrated optics. We then had the pleasure of listening to Dr. Medhi Saligane talk on agent AI for analog layout generation. Dr. Saligane is now with Brown University in the US. The first day was closed by a talk on memristor modeling by Dr. Arturo Sarmiento from INAOE. Memristors are fast becoming a common element in IC design, and their modeling and eventual characterization has become a very important field of endeavor in recent years.

The second day was opened by Dr. Colin Shaw from Silvaco (US) who gave a deep description of the status of the Si2 Compact Model Coalition.
The rest of the morning was dedicated to a three-hour workshop on digital circuit synthesis using open source CAD/EDA design tools.

Friday's first talk was by Dr. Harriet Parnell, a senior academic engineer at Ansys, and who gave a talk describing Ansys Lumerical FDTD tool, with a case study of a nanohole array. This was followed by a description of logic technology device innovations, given by Dr. Carlos Díaz, the Senior Director for Research and Development for Taiwan Semiconductor Manufacturing Company (TSMC). This great talk was followed by a presentation of the MOSbius project given by Dr. Peter Kinget, the Bernard J. Lechner Professor of Electrical Engineering at Columbia University. The workshop was closed by a researcher at INAOE, Dr. Reydezel Torres, who spoke of the simulation of chip-to-chip interconnects, another very important aspect of semiconductor technology.

The MOS-AK INAOE workshop was attended by 86 participants, mostly undergrad students but also by professional academicians and scientists. We can call it a success, and we hope that it has contributed to the country's much-needed progress in integrated circuit design and technology.

-- R.Murphy and W.Grabinski 
-- on the behalf of the MOS-AK INAOE Organizing Committee

Enabling Compact Modeling R&D Exchange

RM/WG120625

Jun 11, 2025

[mos-ak] [C4P] 9th Sino MOS-AK Workshop Shenzhen, August 14-16, 2025

Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
9th Sino MOS-AK Workshop Shenzhen
August 14-16, 2025

Announcement and C4P

The International MOS-AK Workshop will be held on Aug. 14-16th, 2025 on- the beautiful campus of the Southern University of Science and Technology (SUSTech), Shenzhen, China. With the aggressive scaling of CMOS technologies and constantly emerging diversified devices, accurate device modeling technique poses severe challenge to circuit and system designers, in particular for RF/MW/mmW/THz/Power/optics. The workshop aims to strengthen a network and discussion forum for experts in the field, provide a forum for the presentation and discussion of the leading-edge research and development results of analytical modeling, compact modeling, characterization and simulation techniques for advanced devices, circuits and technologies. In addition to regular papers, MOS-AK Shenzhen 2025 will host three tutorial/workshop sessions on advanced GaN device modeling and circuit design, cryogenic CMOS modeling and circuit design, and millimeter-wave radar applications.   

Paper Submission: Authors from both academia and industry are invited to submit technical papers describing original work and/or advanced practices and R&D projects

(any related enquiries can be sent to music@sustech.edu.cn)

Online Registration is open (any related enquiries can be sent to music@sustech.edu.cn)

Important Dates:
  • Manuscript submission deadline: 30th June 2025
  • Notification of Acceptance: 10th July 2025
  • Submission of final manuscript: 15th July 2025
  • MOS-AK Workshop:  Aug. 14-16th, 2025
-- Xiaoguang Liu, SUSTech and W.Grabinski for Extended MOS-AK Committee
WG110625
 

Jun 3, 2025

[mos-ak] [2nd Announcement] MOS-AK Workshop, London, July 11, 2025

Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
MOS-AK Workshop, London, July 11, 2025

2nd Announcement and C4P

The Summer MOS-AK Workshop on Compact/SPICE Modeling will take place on July 11, 2025, at London Met. The Conference Centre, room TM3-03, 166-220 Holloway Road, London. This event is coorganized by London MET with the technical cosponsorship of UK IETE and IEEE EDS. We invite you to join us for MOS-AK workshop and learn from the experts in the field of Compact SPICE modeling, Verilog-A standardization and FOSS CAD/EDA IC design support for OpenPDKs.

Planned Summer MOS-AK Workshop at London MET is a forum to strengthen a network and discussion among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology manufacturers, circuit designers, and CAD/EDA tool developers and vendors supporting foundry/fabless interface strategies with the focus on OpenPDKs (eg: Skywater/GF CMOS, IHP RF BiCMOS) 

Important Dates:
  • 2nd Announcement: June 2025
  • Final Workshop Program: June 30, 2025
  • MOS-AK Workshop: July 11, 2025
MOS-AK/London Speakers Tentative List (alphabetic order):
  • Phillip-Ferreira Baade-Pedersen; IHP
  • Mike Brinson; London MET
  • Patryk Golec; Uni. Paris-Saclay
  • Wladek Grabinski, MOS-AK/IHP
  • Krzysztof Herman; IHP
  • Rohith-Karnati Penchala; Pragmatic Semiconductor Ltd.
  • Radu Sporea; Uni. Surrey
  • Bal Virdee; London MET
Online Abstract Submission is open (any related enquiries can be sent to abstracts@mos-ak.org)

Online Free Registration is open (any related enquiries can be sent to registration@mos-ak.org)

02062025


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[ICFOSS] Bridge Course for Eng/BSc Degree Aspirants

Bridge Course for Engineering/BSc Degree Aspirants - Season III

ICFOSS is organizing a "Bridge Course" for Students who have completed their higher secondary education and aspires to pursue Engineering or BSc degrees in fields such as Computer Science, Electronics, Data Analytics, Physics, Mathematics and Statistics. The course will be conducted in two batches, scheduled from 26th to 31st May 2025 and 9th to 14th June 2025This program mainly aims to provide them with the necessary knowledge, skills, and confidence to excel in various fieldsIt equips them with a strong foundation in Python programming and exposure to FOSS principles, setting them on a path for success and support during this transition period from school to college. This also aims to utilize this waiting period effectively by offering relevant educational activities and resources to help students to bridge the gap and stay engaged academically.

This is a combined course of Introduction to Python and Free and Open Source Software (FOSS), which is designed by ICFOSS to introduce students to Python programming and familiarize them with the concept and usage of free and open source software (FOSS). This program not only enhances their technical skills but also instills values of collaboration, knowledge sharing, and innovation that are essential in the field of technology. By the end of the course, students feels confident and well-prepared to tackle the challenges of college-level programming courses.

Objectives: Skill development and readiness for college- The course aims to develop essential skills required for success in college-level Engineering programs and BSc degrees in fields of Computer Science, Electronics, Data Analytics, Physics, Mathematics, and Statistics. It focuses on improving programming proficiency, logical reasoning, algorithmic thinking, and software development practices. The program also aims to support students, helping them stay motivated, engaged, and prepared for their upcoming BSc degrees or engineering programs.

Course Highlights: Live Classes, Structured curriculum by industry veterans, Customized for time flexibility, Custom learning path, Practical experience through simulations and project.

Mode of training: This training program is conducting in offline mode and our systematic approach includes skills assessment, intensive trainings and mentoring that helps valuable learning opportunities and unwavering support to students during this transition period.

Topics:

a) Introduction to Python : Introduction to Programming, Variables and Data Types, Control Flow and Decision Making, Lists, Tuples, and Dictionaries, Functions and Modules, File Handling, Object-Oriented Programming (OOP) Basics, Exception Handling, Deployment Using Flask, Working with External Libraries , Introduction to AI Concepts (Basics of AI, ML overview, Real-world Applications), Flask Project (Hands-on).

b) Free and Open Source Software: Introduction to FOSS, Linux Installation and Basics, Command-Line Basics, User and Group Management, Networking and Remote Access, System Services and Process Management, File System and Storage Management, Overview of FOSS Distros, Products, and Tools.

Target Audience: It is open to students who have completed their higher secondary education and aspires to pursue Engineering or BSc degrees in fields such as Computer Science, Electronics, Data Analytics, Physics, Mathematics, and Statistics.

Prerequisites: It is expected that students have a fundamental understanding of using computers.

Dates:

Name of Program

Dates

Time

Registration Fee

Batch 1

From 26th to 31st May 2025

10.00AM to 5.00 PM

Rs. 4,000/-

Batch 2

From 9th to 14th June 2025

Application Process: 

The number of participants is limited to 30 No.s per batch, on a first-come first-serve basis.

Course Duration: Total of 6 Days (6Hrs/Day)

Registration Fee: Rs. 4,000/-

Application deadline : 07th June 2025

For online payment, the bank accounts details of ICFOSS is provided below:

Account Name

ICFOSS

Account Number

67242303296

IFSC

SBIN0070737

Name of Bank

State Bank of India

Branch

Technopark, Thejaswini, Thiruvananthapuram

For Registration, follow: https://applications.icfoss.org/bridge-course-2025/
Please contact +91 7356610110 | +91 471 2413012 /13 /14 | +91 9400225962
between 10:00-17:00 hrs) for further clarifications.