[paper] 60GHz Class-AB PA in 22nm FD-SOI CMOS

Dimitrios Georgakopoulos, Vasileios Manouras and Ioannis Papananos

A 60-GHz Current Combining Class-AB Power Amplifier in 22 nm FD-SOI CMOS

Microwave 2026, 2(1), 2; DOI: 10.3390/microwave2010002

* School of Electrical and Computer Engineering, National Technical University of Athens, (GR)

Abstract: This work presents a fully integrated, two-stage, deep class-AB power amplifier (PA) operating at a center frequency of 60 GHz. High efficiency and suppression of third-order intermodulation products are targeted, achieving improved linearity compared to reported state-of-the-art designs. A current combining architecture is also employed to enhance the output power capability. The PA is designed in a 22 nm FD-SOI CMOS technology and is optimized through a complete schematic-to-layout design flow. Post-layout simulations indicate that the PA achieves a peak power-added efficiency (PAE) of 28%, a saturated output power ( 𝑃𝑠𝑎𝑡 ) of 20.2 dBm, and a maximum large-signal gain (𝐺𝑚𝑎𝑥 ) of 19.6 dB at 60 GHz, evaluated at an operating temperature of 60 °C. The design maintains high linearity across the targeted output power range, exhibiting effective suppression of third-order intermodulation distortion (IMD3), which enhances its suitability for spectrally efficient modulation schemes. 

FIG: Top-level schematic of the overall mm-Wave PA, including layout of all passive networks

[paper] Compact IV Model for DG MoS2 FETs

Ahmed Mounir, Francois Lime, Alexander Kloes, Alexandros Provias, Theresia Knobloch, 

K. P. O’Brien, Tibor Grasser and Benjamin Iniguez

Compact I–V Model for Double-Gated MoS2 FETs Including Short-Channel Effects

IEEE TED, Vol. 72, No. 12, Dec 2025

DOI: 10.1109/TED.2025.3622099

Rovira i Virgili University, Tarragona (SP)
THM University of Applied Sciences, Giessen (D)
Technical University of Vienna (A)
Intel Foundry Technology Research, Hillsboro (US)

Abstract: This article presents a physics-based analytical compact model for double-gated molybdenum disulfide (MoS2) field effect transistors (FETs), incorporating key physical and short-channel effects (SCEs), such as mobility degradation and velocity saturation. The model is developed from a unified charge control model by evaluating the charge density within the 2D MoS2 layer, represented using the Lambert W function, which provides an analytical expression valid and continuous from the subthreshold to the above threshold regime. The drain current is then derived from this unified charge control model, and as a function of closed-form equations for the charge densities at the source and drain ends of the channel. Despite its simplicity, the model shows excellent agreement with experimental data for channel lengths down to 60nm, making it a powerful tool for accurately predicting the performance of downscaled devices. By including SCEs, this work extends previous modeling efforts and provides a more comprehensive framework for the simulation and optimization of 2D material-based FETs in circuit design.

FIG: Cross-sectional view of the double-gated MoS2 FET, showing the top gate oxide stack made of Al2O3 and HfO2, with the local back gate oxide consisting of HfO2. Validation of the compact model against experimental data for double-gate MoS2 FET L = 60nm (bottom line)

Acknowledgements: This work was supported in part by European Union Bayesian inference with flexible electronics for biomedical applications (BAYFLEX) under Contract 101099555 and in part by the Ministry of Science of Spain under Contract PID2021122399OB-I00

[book] CMOS RF and mm-Wave Transceivers and Synthesizers

CMOS RF and mm-Wave Transceivers and Synthesizers

(1st ed. 2025)

By Bharatha Kumar Thangarasu, Nagarajan Mahalingam, 

Kaixue Ma, Kiat Seng Yeo

Jenny Stanford Publishing

DOI 10.1201/9781003673569

Abstract: Power consumption has become a critical concern in RF/mm-wave integrated circuit (IC) design thanks to new applications from 5G, mobile computing, artificial intelligence, and the Internet of Things. However, big challenges lie ahead for chip designers when they choose to develop ICs using silicon technology for low-power and high-data-rate applications. This is because silicon technology suffers from undesirable energy dissipation due to its lossy substrate and high resistive wiring loss at GHz frequencies. Nonetheless, silicon remains the most suitable material, satisfying the demands of a rapidly growing semiconductor market through low fabrication cost and ease of achieving system-on-chip or system-in-package integration. While long being neglected, low-power RF/mm-wave design has vaulted to the forefront of attention in recent years due to the demand for ultra-low-power transceivers to achieve sustainability. Designing genuinely ubiquitous transceivers for these new applications requires innovations in both system architecture and circuit implementation.

This book closes the gap between a typical textbook with theories that are difficult to understand and a design-oriented book that offers little insight into actual theories. It evaluates and discusses different circuit topologies, receiver and transmitter architectures, phase-locked loop performance metrics, phase noise analysis, and sub-system-level designs that have yet to be reported in other books.

Table of Contents

• Chapter 1: CMOS RF Active and Passive Devices (pp. 1–49)
• Chapter 2: Transceiver Building Blocks (pp. 50–126)
• Chapter 3: Receiver Sub-System (pp. 127–193)
• Chapter 4: Transmitter Sub-System (pp. 194–238)
• Chapter 5: Transceiver System Integration (pp. 239–347)
• Chapter 6: CMOS RF/mm-Wave Oscillators (pp. 348–401)
• Chapter 7: CMOS Frequency Synthesizers (pp. 402–482)

[open source hardware] selected examples

 SemiCoLab - Multi-project platform on ASIC

SemiCoLab is an educational project that seeks to democratize the complete integrated circuit design process. It allows students, teachers, and enthusiasts to design digital logic with open-source tools and fabricate it on a multiproject wafer, sharing costs and accelerating hands-on learning.

VSDSquadron Mini - RISC-V Development Kit

The VSDSquadron Mini, a versatile powerhouse within the RISC-V landscape that elevates your development to new heights. Whether you’re a newcomer delving into the realm of embedded systems or an experienced developer crafting an intricate device, the VSDSquadron Mini is your ideal companion. It seamlessly bridges the gap between theory and practical application, offering an on-board flash programmer with single-wire programming protocol to jumpstart your projects in education and development with proficiency and ease.

Watchy - A fully open source & customizable E-Ink watch

Watchy is an E-Ink watch with open source hardware and software. It has a barebones design utilizing the PCB as the watch body, allowing it to be worn as-is, or further customized with different 3D printed cases and watch straps. It is a unique timepiece that is also a wearable development platform, allowing users to create their own experience.

[paper] Open Source EDA Tools in ASICs

Édney M. V. Freitas, Nicolas Guimarães, Rafael Maria, Felipe Costa, 

Guilherme Milani, Bruno Sanchesand, Wilhelmus Van Noije

Using Open Source EDA Tools in ASICs for HEP: A Mixed Comparison

arXiv:2512.06122v1 [hep-ex] 5 Dec 2025

1. Escola Politécnica da Universidade de São Paulo, Brazil

Abstract: This work compares open-source electronic design automation tools with a commercial environment using three representative integrated circuit blocks in the IHP 130nm open PDK: a common-mode noise filter, a finite-state machine, and a voltage-controlled oscillator. The study reports design effort and quality of results for digital logic, including area, power, and timing closure, and examines analog layout feasibility. For the finite-state machine at 50 MHz, the open-source flow reached 0.029 mm2 (post-layout) and 4.37 mW (estimated) with 828 standard cells, whereas the commercial flow achieved 0.019 mm2 and 2.00 mW with 497 cells, corresponding to increases of 53% in area and 118% in power. The common-mode noise filter totals 1.879 mm2 with 1703 flipflops at 50 MHz. The voltage-controlled oscillator occupies 0.0025 mm2 and achieves a simulated maximum oscillation frequency of 2.65 GHz. The contribution is a side-by-side quantification of quality of results across digital and analog blocks in the IHP open PDK. The results indicate that open-source tools are viable for early prototyping, training, and collaboration, while commercial flows retain advantages in automation and quality of results when strict targets on power and area or precision analog layout are required.

FIG: Digital layouts under identical constraints. Layer colors are tool specific.

Acknowledgments: This work was financed, in part, by the São Paulo Research Foundation (FAPESP), Brazil, Grants #2024/04802-9 and #2024/06703-8, by CNPQ Grant #134869/2024-9. This study was financed in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES), Brazil - Finance Code 001.

Fwd: EUROSOI-ULIS 2026: Call for papers

On behalf of the Organizing Committee, it is our great pleasure to announce the 12th Joint EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS 2026), which will take place from May 20 to 22, 2026, in Granada, Spain.

This conference aims to bring together scientists and engineers in an interactive forum to discuss SOI technology and advanced microelectronic devices. A key objective is to foster collaboration and partnerships among academia, research institutions, and industry stakeholders in the field.

We warmly invite students and researchers from both academic and industrial backgrounds to submit their abstracts and join us in Granada. The conference offers an excellent opportunity to engage with colleagues, share knowledge, and experience the charm of this marvelous city.

We are also pleased to announce that the "IRDS & ISRDS workshop" will take place as a satellite event on 18–19 May at the same venue. This event will be an opportunity to dive into the heart of semiconductor innovation — to explore emerging directions in computing, and in materials and devices for computing — with expert-led sessions. Participation will be free of charge.

Abstract submission link: https://easychair.org/conferences?conf=eurosoiulis2026
Template: https://wpd.ugr.es/~eurosoiulis2026/wp-content/uploads/2025/07/EUROSOI-ULIS2026_Abstract_Template.docx

Important dates
- Abstract submission deadline: February 15, 2026
- Notification of acceptance: March 31, 2026
- Registration opening: March 1, 2026
- Early Bird Registration Deadline: April 20, 2026

Venue
The conference and the satellite workshop will be held in the Assembly Hall of the Facultad de Medicina of the Universidad de Granada (UGR). The Faculty of Medicine is located in the modern Parque Tecnológico de Ciencias de la Salud (PTS), a state-of-the-art campus that combines modern infrastructure with a comfortable, accessible environment, ideal for a scientific meeting like ours.

Selected papers will be published as 4-page letters in a Special Issue of Solid-State Electronics (Elsevier).

Two awards have been organized already:
- The "Androula Nassiopoulou Best Paper Award" attributed by the SINANO Institute.
- A best poster award attributed by Solid-State Electronics journal (Elsevier).

In addition to the technical program, we aim to offer an enriching cultural and historical experience for all attendees.

For more details, please see the attached call for papers or visit the conference website at:
https://eurosoiulis2026.ugr.es/

Future updates will also be posted on the website.

Best regards,
EuroSOI-ULIS 2026 Local Organizing Committee
eurosoiulis2026@ugr.es
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[paper] Single Event Upset in FINFET SRAM

SUN Qian¹²,, GUO Yang¹²*,, LIANG Bin¹², CHI Yaqing¹², TAO Ming³, LUO Deng¹², CHEN Jianjun¹², SUN Hanhan2, HU Chunmei¹2, FANG Yahao¹2, GAO Yulin¹2, XIAO Jing³

Process fluctuation influence on single event upset in sub-20 nm FinFET SRAM

中图分类号:TN405 文献标志码:A 文章编号:1001 - 2486 (2025)06 – 264 - 10 

1. College of Computer Science and Technology, National University of Defense Technology, Changsha 410073, China;
2. Key Laboratory of Advanced Microprocessor Chips and Systems, National University of Defense Technology, Changsha 410073, China;
3. College of Electrical and Information Engineering, Hunan University, Changsha 410082, China

Abstract: To investigate the process fluctuation influence on SRAM (static random-access memory) single event upset in sub-20nm FinFET (fin field-effect transistor) process, a high precision 3D TCAD model based on commercial process fluctuations was established, then simulated to find the FinFET SRAM single event upset threshold under different process corners. The simulation results show that the FinFET SRAM upset threshold has less variation induced by process corner fluctuation. Then, to understand the impact of specific process parameter fluctuations on the single event upset threshold, the process fluctuation factor impact on single event upset was discussed, including fin width, fin height, the oxide thickness and the work function fluctuation. The simulation results show that the first two factors did not affect the upset threshold, while the latter two factors caused slight fluctuations in the upset threshold. Significant reduction in the impact of process fluctuations on FinFET SRAM single event upset threshold is firstly found, which is of great significance for the development of highly consistent radiation hardened aerospace integrated circuits.  

Fig: Electron density snapshot when heavy-ion hit point A with 7 MeV · cm²/mg

[paper] Low-Frequency Noise in Single-Layer Graphene FETs

An extended low-frequency noise compact model for single-layer graphene FETs 

including correlated mobility fluctuations effect

Nikolaos Mavredakis, Anibal Pacheco-Sanchez, and David Jiménez

https://arxiv.org/pdf/2512.08388

Departament d’Enginyeria Electrònica, Escola d’Enginyeria, Universitat Autònoma de Barcelona, Bellaterra 08193 (SP)
Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, 18011 Granada (SP)

Abstract: Correlated mobility fluctuations are considered in the physics-based carrier number fluctuation (ΔΝ) low-frequency noise (LFN) compact model of single-layer graphene field effect transistors (GFET) in the present study. Trapped charge density and Coulomb scattering coefficient ΔΝ LFN parameters are obtained after applying a parameter extraction methodology, adapted from conventional silicon technologies,to the linear ambipolar regions of GFETs. Appropriate adjustments are considered in the method according to GFETs’physical characteristics. Afterwards, Hooge mobility as well asseries resistance fluctuations LFN parameters can be extracted.The updated LFN model is validated with experimental data from various long and short-channel GFETs at an extendedrange of gate and drain bias conditions.

Fig: SID2/ID2 vs. VGS at 1 Hz for B (a) and A (b) -type RF GFETs with W=12μm and L=100nm

at VDS=60 mV. Markers: measurements, solid lines:model, dashed lines in (b): 

θint=0 V-1. Different colors represent different LFN contributions.

Acknowledgments: This work has received funding from the European Union’s Horizon2020 research and innovation programme under grant agreements NoGrapheneCore3 881603, from Ministerio de Ciencia, Innovación y Universidades under grant agreements RTI2018-097876-B-C21(MCIU/ AEI/ FEDER, UE), PID2021-127840NB-I00(MCIN/AEI/FEDER, UE), and CNS2023-143727 RECAMBIO (MCIN/AEI/ 10.13039 /501100011033). 

This work is also supported by the European Union Next Generation EU/PRTR research project.

[mos-ak] [Final Program] MOS-AK LatAm Webinar, Dec. 12, 2025

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

MOS-AK LatAm Workshop

(online), Dec. 12, 2025

The End‑of‑Year MOS-AK Workshop/Webinar on Compact/SPICE Modeling will be held online on Dec. 12, 2025. We invite you to join this webinar to learn from the experts in Compact SPICE modeling, Verilog‑A standardization, and FOSS CAD/EDA IC design support for OpenPDKs, internationally, with particular focus on Latin America

Venue: MOS-AK LatAm (Webinar)
Online Webinar Access Link: https://meet.jit.si/MOS-AK_LA_2025

• Final Workshop Program: Dec. 12 2025
San Francisco, 09:00 - 11:00
Rio de Janeiro, 14:00 - 16:00
Geneve, 18:00 - 20:00

T_1	OpenPDK LatAm Krzysztof Herman IHP (D)
T_2	AI/ML-Driven Device Modeling for Advanced Nodes, RF and Power Applications Fahad Usmani Keysight Technologies (US)
T_3	Design and Integration of Multiple Open-Source Analog Circuits Fabricated in SKY130 Technology within Silicluster v2 Uriel Jaramillo Toral* Hector Emmanuel Muñoz Zapata and Susana Cisneros Ortega CINVESTAV (MX)
T_4	SemiCoLab, A Multi-Project ASIC Platform for Democratizing Chip Design Emilio Baungarten, Susana Ortega, Miguel Rivera, and Francisco Javier CINVESTAV (MX)
T_5	Building an Ecosystem Through IC Education in Colombia: A Model for Emerging Semiconductor Regions Juan Sebastián Moya Baquero SymbioticEDA
T_6	Silicon-Proven Learning With OpenPDKs and MPW Access for IC Education Eduardo Holguin Weber Universidad San Francisco de Quito (EC)
T_7	OpenPDK Mismatch Testchip Juan Pablo Martinez Brito CEITEC S.A. (BR)
T_8	Physics-Based Modeling and Charge Density Saturation in GaN/AlGaN MOS-HEMTs Ashkhen Yesayan, Farzan Jazaeri, Jean-Michel Sallese EPFL (CH)

W.Grabinski for Extended MOS-AK Committee

WG111225

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[paper] Noise Propagation and Statistic Variability in MOSFETs

Raphael Chatzipantelis, Loukas Chevas, Nikolaos Makris and Matthias Bucher

Noise Propagation and Statistic Variability in MOSFETs Using Probability Density Functions

Fluctuation and Noise Letters (Accepted Paper)

DOI: 10.1142/S0219477525400255

1) School of Electrical and Computer Engineering, Technical University of Crete, Chania 73100, Greece
2) Foundation for Research and Technology Hellas, Heraklion 70013, Greece,

Abstract: Probability density functions using stochastic methods are shown to be an effective tool in the context of MOSFET noise and variability modeling. These methods are employed here in the context of the charge-based EKV MOSFET model. As an example, a Gaussian noise density function applied at the gate or the source of a MOSFET causes a corresponding drain current noise density function, which may be expressed analytically as a function of inversion coefficient only. The same expression may be used to model drain current variability due to MOSFET parameters such as threshold voltage. Furthermore, the method is extended to variations of quantities such as transconductance and transconductance-to-current ratio. The method shows promise in variability modeling of MOSFETs and may complement traditional approaches.

FIG: Comparing the traditional ”small-signal” transconductance method with the stochastic PDF method for 𝑖𝑓, derived from the charge-based model, where in both cases the same noise (or variability) at the gate is applied (𝑉𝐺= 87mV, 𝜎𝑉𝐺=10mV), centered at 𝑖𝑓=2, showing slightly different mean and ±3𝜎 values, while the tail distributions differ significantly.

Acknowledgements: The authors gratefully acknowledge Dr. Predrag Habas from EM Microelectronic S.A. for valuable discussions and wafers for noise and statistical analysis. This work was partly funded by the European Union, and by Greek National funds, under the topic DIGITAL- Chips-2024-SG-CCC-1 - Competence Centers, Project No 101217803 - HCCC.

[semiwiki] Revolution EDA

Revolution EDA: A New EDA Mindset for a New Era

by Semiwiki Admin in Category: EDA on 11-17-2025 at 6:00 am

Key Takeaways

• Revolution EDA introduces an open-source core platform inspired by Visual Studio Code, allowing rapid development and integration with modern machine learning workflows.
• The platform uses JSON for design data storage, making it AI-readable and eliminating data format friction, which contrasts with traditional binary databases.
• Revolution EDA provides a complete front-end design environment with advanced schematic and layout editors, incorporating Python for dynamic functionalities.

Murat Eskiyerli, PhD, is the founder of Revolution EDA  with the tagline “A new EDA mindset for a new era.”  The revolution won’t happen overnight. But it has to start somewhere [ read more... ] 

[mos-ak] [Announcement] MOS-AK LatAm Webinar, Dec. 11-12, 2025

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

MOS-AK Workshop

LatAm (online), Dec. 11-12, 2025

The End‑of‑Year MOS-AK Workshop/Webinar on Compact/SPICE Modeling will be held online on December 11–12, 2025. We invite you to join this webinar and learn from experts in Compact SPICE modeling, Verilog‑A standardization, and FOSS CAD/EDA design support for OpenPDKs. The MOS-AK LatAm Workshop provides a forum to: Strengthen networks and discussions among experts in compact/SPICE modeling; Promote open information exchange on Verilog‑A standardization; Connect academic and industrial specialists in the modeling field; Gather feedback from technology manufacturers, circuit designers, and CAD/EDA tool developers supporting foundry/fabless interface strategies with a focus on OpenPDKs (e.g., Skywater/GF CMOS, IHP RF BiCMOS)

 

Important Dates:

• 1st Announcement: Nov. 2025
• Final Workshop Program: Dec.1 2025
• MOS-AK LatAm online/webinar: Dec. 11-12, 2025

MOS-AK/LatAm Speakers Tentative List (alphabetic order):

• Sergio Bampi, Mateus Grellert and team at UFRGS (BR)
• Juan Pablo Martinez Brito, CEITEC S.A. (BR)
• Carlos Galup, Márcio Cherem Schneider and team at UFSC (BR))
• Krzysztof Herman, IHP (D)
• Eduardo Holguín and team at Universidad San Francisco de Quito (EC)
• Uriel Jaramillo and team from CINVESTAV (MX)
• Peter Lee, Si2 CMC Chair (US)
• Jorge Ivan Marin Hurtado, Universidad del Quindío (CO)
• Mehdi Saligane, Uni. Brown (US) IEEE SSCS TC-OSE Chair
• Fahad Usmani, Keysight (US)

Online Abstract Submission will be open (any related enquiries can be sent to abstracts@mos-ak.org)
Online Free Registration will be open (any related enquiries can be sent to registration@mos-ak.org)

W.Grabinski for Extended MOS-AK Committee

WG221125

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[C4P] ICMC2026 Submission Deadline: February 1, 2026 (4-page paper)

ICMC2026 | July 30-31, 2026| Long Beach, CA

Call for Papers
Submission Deadline: February 1, 2026  (4-page paper)

The Compact Model Coalition (CMC) brings academia and industry partners together in the development and standardization of compact models for semiconductor devices. For more than 30 years, the CMC has been instrumental in creating standardized and verified models for designers to use in their increasingly complex circuits for SPICE simulation. The CMC is organizing the second edition of the International Compact Modeling Conference, cosponsored by IEEE EDS. It will focus uniquely on compact device models, their development, and broad application in the semiconductor industry. You are invited to participate in the evolution of these models, guiding model development to help circuit designers achieve the best circuit performance possible, and enabling foundries to leverage the strength of their device fabrication to the full extent. Join world experts in design, process technology, and model development for a two-day in-person event to discuss state-of-the-art semiconductor device modeling, offering a rare opportunity to present and learn about this core element of circuit design and how to get the most from these global collaborations.

 
HIGHLIGHTED THEMES FOR ICMC 2026 

This year, ICMC especially encourages submissions in the following domains: 

• Electrostatic Discharge (ESD) modeling for protection design
• Modeling of parasitic BJT activation, snapback behavior, ESD stress and breakdown, transient response, failure prediction, etc.
• Reliability and aging-aware compact models and simulation techniques
• for degradation mechanisms such as Bias Temperature Instability (BTI), Hot Carrier Degradation (HCI), Time Dependent Dielectric Breakdown (TDDB)
• self-heating and circuit reliability prediction
• AI or Machine Learning for model development, parameter extraction, circuit simulation efficiency, etc. 

GENERAL TOPICS 

 We are also seeking submissions in the following domains.

Application of Device Models Innovative application of CMC standard device models Designer's perspective: best practices, novel use, and benefits of standard device models to improve circuit design and system performance. Use of compact models to demonstrate foundry device capabilities Device Model Development Modeling of physical phenomena: Statistical variation, noise and fluctuations, RF and high-frequency effects, layout effects, etc. Methodologies to assist in model development, practices for coding, quality assurance, circuit simulator integration, etc. Parameter extraction, measurement techniques, model calibration, validation, and verification methodologies.	Model Enhancements and Implementations Model extensions to capture additional device features (leakage, capacitance, second-order dependencies)or expand the operating range of existing devices (bias, power, temperature, frequency, etc.) Model enhancements to support the design of new or demanding circuits Model workflow, implementation, and integration into the design environment (PDK) Computing/simulation platforms, simulation algorithms, and methodologies to improve simulation performance (parallel processing, etc.) Models for established device types that currently lack standardization. Emerging devices Modeling of emerging and future devices:compact models for novel device technologies and architectures that could further revolutionize circuit performance and design flow. For example, complementary FET, ferroelectric devices, silicon photonics, MRAM, RRAM, cryogenic, quantum computing, 2D-materials, oxide semiconductors, etc.
IMPORTANT DATES February 1, 2026 Submission deadline  (4-page paper) April 6, 2026 Acceptance notification May 10, 2026 Final version for publication July 30-31, 2026 Conference takes place For more details, visit: 2026.si2-icmc.org	ICMC2026 COMMITTEE General Chair: Shahed Reza (Sandia National Laboratories) Vice Chair: Harshit Agarwal (IIT Jodhpur) Technical Program Chair: Gert-Jan Smit (NXP) Technical Program Vice-Chair: Girish Pahwa (NYCU Taiwan) Treasurer: Leigh Anne Clevenger (Si2) Publicity Committee Chair: Wladek Grabinski (MOS-AK)

[C4P] Exploring Beyond-CMOS Paradigms for Energy-Efficient Computing

Exploring Beyond-CMOS Paradigms for Energy-Efficient Computing

Call for Papers

Excited to announce that our Research Topic is now open for submissions! As CMOS technology reaches its limits, emerging devices like NCFETs, TFETs, spintronic systems, 2D materials, wide-bandgap semiconductors, and MEMS are paving the way for next-generation low-power computing. We invite Original Research, Reviews, Mini-Reviews, and Perspectives from researchers working on innovative materials, devices, models, circuits, and system-level demonstrations.

• Summary Deadline: 13 Feb 2026
• Manuscript Deadline: 29 May 2026

Let’s push the boundaries of energy-efficient, beyond-CMOS electronics together! Submit your work and be part of this emerging frontier.

Call for Papers - Frontiers in Electronics with Impact Factor: 2.1

Topic editors

Fabrizio Bonani, Polytechnic University of Turin (IT)

Mariana Amorim Fraga, School of Engineering, UPM, São Paulo, (BR)

Sonal Shreya, Aarhus University (DK)

Abhishek Acharya, Sardar Vallabhbhai National Institute of Technology Surat (IN)

Topic coordinator

Khoirom Johnson Singh, Dhanamanjuri University, Imphal, Manipur (IN)

[IEEE EDS DL] Multifunctional materials for emerging optoelectronic technologies

IEEE EDS Distinguished Lecture

Hawaii Section Jt. Chapter, ED15/SSC37

December 19 @ 6:30 pm - 8:00 pm

Room: 244, Bldg: Holmes Hall, 2540 Dole St, Honolulu

Hawaii, United States, 96822

Dr. Federico Rosei from the University of Trieste will be presenting a Distinguished Lecturer Seminar titled "Multifunctional materials for emerging optoelectronic technologies" on Friday December 19th at 6:30PM. RSVP one week in advance for a headcount on food [register]

Abstract: functionalities. Such systems are then used as building blocks for the fabrication of various emerging technologies. In particular, nanostructured materials synthesized via the bottom–up approach present an opportunity for future generation low cost manufacturing of devices. We focus in particular on recent developments in solar technologies that aim to address the energy challenge, including third generation photovoltaics, solar hydrogen production, luminescent solar concentrators and other optoelectronic devices. 

Bio: Federico Rosei (MSc (1996) and PhD (2001) from the University of Rome “La Sapienza”) holds the Chair of Industrial Chemistry at the Department of Chemical and Pharmaceutical Sciences, University of Trieste since March 2023. Previously he was Full Professor at the Centre Énergie, Matériaux et Télécommunications, Institut National de la Recherche Scientifique, Varennes (QC) Canada, where he served as Director (07/2011–03/2019). He held the Canada Research Chair (Junior) in Nanostructured Organic and Inorganic Materials (2003–2013) and the Canada Research Chair (Senior) in Nanostructured Materials (2016–2023) and the UNESCO Chair in Materials and Technologies for Energy Conversion, Saving and Storage (2013–2023).

[paper] Compact Wide-Band Antenna

A. Anand Babu, K. Thenmalar

Design and Evaluation of a Compact Wide-Band Antenna for Wearable Wireless Applications

Tehnički vjesnik 32, 6(2025), 2437-2442

Original scientific paper DOI: 10.17559/TV-20241128002156

ECE, Vivekanandha College of Technology, Tiruchengode, Tamil Nadu, India
EEE, Vivekanandha College of Engineering for Women, Tiruchengode, Tamil Nadu, India

Abstract: This article presents a compact wide-band antenna designed for emerging wireless applications. The antenna utilizes a fiberglass-reinforced (FR4) substrate material with a thickness of 1.6 mm as its base. By varying the length and side edge dimensions of the antenna element, the design achieves a wide operational bandwidth ranging from 3.2 to 3.8 GHz, covering all new radio bands. Experimental optimization of various parameters has been conducted to ensure precise tuning within the desired frequency range. The antenna exhibits a uniform radiation pattern across its operating band, ensuring stable performance. Specific Absorption Rate (SAR) evaluations, conducted as per the Federal Communications Commission (FCC) guidelines, confirm the SAR values remain within the prescribed safety limit of 1.6 W/kg when the antenna is positioned on a human phantom model. The proposed antenna also demonstrates high radiation efficiency and peak gain, making it suitable for wearable applications where compact size and reliable performance are critical. This innovative design addresses the growing demand for wide-band antennas in wireless communication systems, emphasizing safety, efficiency, and adaptability for wearable technologies.

Fig: Electric field distribution over the radiating circle at (a) 3.45 GHz; (b) 3.7 GHz

(c) - (d) fabricated antenna images

[Free Session] Tokai Rika OpenPDK

Tokai Rika Shuttle Open PDK Commentary Free Session

Saturday, December 13, 2025 13:00~17:00 [and online]

WeWork Hibiya FORT TOWER 9th Floor, Conference Room 9R

1-1 Nishi-Shimbashi, Minato-ku, Tokyo

Time	Speaker	Topic
12:50	ISHI Club	1F Gathering
13:00	ISHI Club	Opening
13:00-13:30	OpenSUSI	Overview of Tokai Rika Shuttle PDK and future plans
13:30-14:30	jun1okamura	Outline of the production of DRC and LVS of Tokai Rika Shuttle PDK and explanation of contents
14:30-15:00	OpenSUSI	Break & Information Exchange
15:00-15:30	Mitch Bailey	Detailed explanation of LVS (Japanese lecture)
15:30-16:00	Hota (SIG's Playground)	How to 🚶 walk through open source PDK: "What is PDK in the first place?" "Where do you want to "read" PDK? "If you want to make your own PDK, where do you start?" and "Examples of what you have done so far".
16:00-16:30	OpenSUSI	PDK Conversation: jun1okamura x Hota x Mitch Bailey: Mr. Hota, an expert in commercial PDK development at a major domestic company, and Mitch Bailey, an expert in open PDK who has been performing structural checks and PDK maintenance of GDS submitted by eFabless, etc.
16:30-17:00	OpenSUSI	PDK Conversation / Honest Edition (No more online streaming will be done from now on): Continuing from the above, we plan to talk about things that cannot be said publicly. In a sense, this may be the real thing.
17:00	ISHI Club	Closing

Discord invitation link 

https://discord.gg/Sj47dJk8x7 

https://discord.gg/RwAWF5mZSR

[Book] Essential Semiconductor Physics

Essential Semiconductor Physics

Mark Lundstrom (Purdue University, USA)

New Era Electronics: A Lecture Notes Series

Pages: 424; October 2025

https://doi.org/10.1142/14454

This book is the fourth volume in the New Era Electronics lecture notes series, a compilation of volumes defining the important concepts tied to the electronics transition happening in the 21st century.

The lectures in this volume are about the underlying physics that makes semiconductor devices possible. The treatment is physical and intuitive; the text is descriptive, not heavily mathematical. The lectures are designed to be broadly accessible to students in science or engineering and to working engineers. They present an electrical engineering perspective, but those in other fields may find them a useful introduction to the approach that has guided the development of semiconductor technology for more than 75 years.

For those who use semiconductor devices, these lectures provide an understanding of the physics that underlies their operation. For those developing semiconductor technologies, these lectures provide a starting point for diving deeper into the physics, chemistry, and materials science relevant to semiconductors. Those who have taken advanced courses will see how specific topics fit into a broader framework. 

Book Sections

Front Matter; pp. i–xvi

Part 1: Materials Properties and Doping

• Lecture 1: Energy Levels to Energy Bands; pp. 3–16
• Lecture 2: Crystalline, Polycrystalline, and Amorphous Semiconductors; pp. 17–27
• Lecture 3: Miller Indices; pp. 29–39
• Lecture 4: Properties of Common Semiconductors; pp. 41–46
• Lecture 5: Free Carriers in Semiconductors; pp. 47–56
• Lecture 6: Doping; pp. 57–75

Part 2: Rudiments of Quantum Mechanics

• Lecture 7: The Wave Equation; pp. 79–99
• Lecture 8: Quantum Confinement; pp. 101–116
• Lecture 9: Quantum Tunneling and Reflection; pp. 117–129
• Lecture 10: Electron Waves in Crystals; pp. 131–145
• Lecture 11: Density of States; pp. 147–164

Part 3: Equilibrium Carrier Concentrations

• Lecture 12: The Fermi Function; pp. 167–177
• Lecture 13: Fermi-Dirac Integrals; pp. 179–190
• Lecture 14: Carrier Concentration vs. Fermi Level; pp. 191–203
• Lecture 15: Carrier Concentration vs. Doping Density; pp. 205–213
• Lecture 16: Carrier Concentration vs. Temperature; pp. 215–228

Part 4: Carrier Transport, Recombination, and Generation

• Lecture 17: Current Equation; pp. 231–250
• Lecture 18: Drift Current; pp. 251–270
• Lecture 19: Diffusion Current; pp. 271–280
• Lecture 20: Drift-Diffusion Equation; pp. 281–288
• Lecture 21: Carrier Recombination; pp. 289–308
• Lecture 22: Carrier Generation; pp. 309–323

Part 5: The Semiconductor Equations

• Lecture 23: The Semiconductor Equations; pp. 327–342
• Lecture 24: Energy Band Diagrams; pp. 343–361
• Lecture 25: Quasi-Fermi Levels; pp. 363–374
• Lecture 26: Minority Carrier Diffusion Equation; pp. 375–396

Back Matter; pp. 397–406

[paper] 28 GHz Wireless Channel for a Quantum Computer at 4K

Ama Bandara∗, Viviana Centritto Arrojo∗, Heqi Deng†, Masoud Babaie†, Fabio Sebastiano†, Edoardo Charbon‡, Evgenii Vinogradov∗, Eduard Alarcon∗, Sergi Abadal∗

28 GHz Wireless Channel Characterization for a Quantum Computer Cryostat at 4 Kelvin

arXiv:2510.16962v1 [quant-ph] 19 Oct 2025

∗Nanonetworking Center in Catalunya, Universitat Politecnica de Catalunya, Barcelona (SP)
† Delft University of Technology (NL)
‡ Ecole Polytechnique F ́ed ́erale de Lausanne (EPFL, CH) 

Abstract: The scalability of quantum computing systems is constrained by the wiring complexity and thermal load introduced by dense wiring for control, readout and synchronization at cryogenic temperatures. To address this challenge, we explore the feasibility of wireless communication within a cryostat for a multi-core quantum computer, focusing on wireless channel characterization at cryogenic temperatures. We propose to place on-chip differential dipole antennas within the cryostat, designed to operate at 28 GHz in temperatures as low as 4 K. We model the antennas inside a realistic cryostat and, using full-wave electromagnetic simulations, we analyze impedance matching, spatial field distribution, and energy reverberation due to metallic structures. The wireless channel is characterized through measured channel impulse response (CIR) across multiple receiver antenna positions. The results demonstrate potential for reliable shortrange communication with high Signal-to-Noise Ratio (SNR) and limited sensitivity to positional variation, at the cost of nonnegligible delay spread, due to significant multipath effects.

Fig: Spatial distribution of the electrical field across the cryostat as observed in the cross-section, 
general top view, and top view at the plane of the antennas.

Acknowledgements: Authors gratefully acknowledge funding from the European Commission via projects with GA 101042080 (WINC) and 101099697 (QUADRATURE).

[IEEE EDS MQ] Trends and Challenges in Microelectronics

IEEE EDS MQ “Trends and Challenges in Microelectronics”

Monday, October 13th, 2025

FACULTY OF ELECTRONIC ENGINEERING

University of Niš

Aleksandra Medvedeva 4, Niš, Serbia

8:00 Registration

8:30   Introductory Remarks and Opening Address

D. Danković, University of Niš, Serbia
Z. Marinković, University of Niš, Serbia

Session I: Chairmen: T. Grasser, V. Davidović

8:45   Device Engineering in E.V.E. Era for Sustainable Nanoelectronics and Nanosystems

S. Deleonibus; CEA/LETI, France

9:10 Neuromorphic Technologies for Autonomous Intelligent Systems at the Edge
[online] A. M. Ionescu; Swiss Federal Institute of Technology, Switzerland

9:30 Coffee break

9:40 Contacts at the Nanoscale and for Nanomaterials

H. Wong; University of Hong Kong, Hong Kong

10:05 Unlocking the Potential of Multifunctional Devices

[online] N. El-Atab; KAUST Saudi Arabia

10:25 Coffee break

Session II: Chairmen: H. Wong, D. Danković

10:35 Steep-slope Devices: Prospects and Challenges

E. Gnani; University of Bologna, Italy

11:00 Modeling FinFETs, Nanowires and Stacked Nanosheets with Temperature

[online] A. Cerdeira; CINVESTAV-IPN, Mexico

11:20 Coffee break

11:30 The IHP OpenPDK Initiative: RoadMap Update

W. Grabinski; IEEE EDS R8 Chair

11:55 A Review of Lambert’s W Function Utilization in Nanodevice Modeling

[online]A. Ortiz-Conde; University Simon Bolivar, Venezuela

12:15 Coffee break

12:25 Benchmarking Insulators for Devices Based on 2D Materials

T. Grasser; Technical University of Vienna, Austria

 

[Internship] Open Source CAD Design Flows

A great opportunity at CEA-Leti in Grenoble, France! This 6-month internship focuses on open source CAD design flows with related PDK, targeting final-year engineering or Master 2 students with an analog/digital design profile.

Description

Are you eager to explore the backstage of microelectronics and learn how to turn a circuit design into a chip ready for fabrication? This internship invites you to take on an exciting challenge: setting up and running a complete open source design flow on related process technology, using an existing SAR ADC design as a motivating example.

The core mission is not to redesign the ADC, but to master the flow that makes such a design possible: installing the tools, configuring the PDKs, and validating each step of the process. How do you configure and launch open source EDA tools? How do you run simulations, placement and routing, and physical verification checks? What are the strengths and limitations of open source technologies in microelectronics design IC? You will be encouraged to explore these questions and propose your own answers.

• Starting date: Spring 2026
• Duration: 5-6 months
• Location: Grenoble, France

Your main tasks will include:

• Installing and configuring the open source design environment (PDK, EDA tools, automation scripts).
• Running the design flow on an existing SAR ADC as a case study.
• Carrying out simulation, synthesis, place-and-route, and DRC/LVS verification.
• Identifying bottlenecks and documenting reproducible solutions.

The student will be supported by an experienced team, with close mentoring and external collaborations to enrich your learning. He won't be left alone with the complexity of the flow – he will be guided, encouraged to test, and empowered to take initiatives. Indicative time allocation: ~30% installation and flow automation, 30% simulation and verification, 30% design adaptation, 10% analysis and scientific dissemination.

Candidate Profile

You are a master's student in microelectronics, embedded systems, or related fields. You have basic knowledge in digital/analog design, simulation, or VLSI concepts. You have basic experience writing scripts in bash/csh and are comfortable working in a Linux environment.

Supervisors: 

Youcef Fellah & Guillaume Regis

To apply, please contact: <youcef.fellah@cea.fr>