[mos-ak] [OpenPDK] IHP Analog Academy

IHP Analog Academy

https://lnkd.in/eQnNX4ug

We, IHP Analog Academy, are excited to present this deep dive into analog, RF, and mixed-signal IC design, powered by open-source FOSS CAD/EDA tools and the IHP Open PDK.

This hands-on course is designed for engineers, researchers, and students eager to gain practical experience with the SG13G2 process at the 130nm technology node. Originally hosted on-site at IHP in Frankfurt (Oder), participants spent five intensive days exploring everything from fundamental analog simulation to advanced RF, 3D EM modeling, and mixed-signal integration. And now we're excited to release it to the open-source community!

The course covers:

- Bandgap reference design and simulation using the gm/Id methodology

- RF design of a 50 GHz Medium Power Amplifier with EM simulation

- Mixed-signal integration and verification of an 8-bit SAR ADC

Each module emphasizes a real-world design flow using tools like:

ngspice, Xyce, KLayout, OpenEMS, QUCS, and Python for data analysis.

Over time, we will expand the repository with:

- More modules

- Updated toolchain support

- Improvements to existing flows

Explore the IHP Open PDK:

- Open PDK GitHub Repository https://github.com/IHP-GmbH/IHP-Open-PDK 

- Interactive Help via ChatGPT https://chat.openai.com

Note: This is not an introductory IC design course. A basic understanding of electronics and microelectronics is assumed. We're proud to contribute this initiative to the community to help lower the barrier to IC design using open-source tools. We encourage contributions via GitHub Issues or Pull Requests! Your feedback and contributions, are welcome!

Lead Author: Phillip Ferreira Baade-Pedersen

Co-Author: Christian Wittke

The Development of this course is funded by the public German project FMD-QNC (16ME083) from BMFTR (Federal Ministry of Research, Technology and Space / Bundesministerium für Forschung, Technologie und Raumfahrt): https://www.elektronikforschung.de/projekte/fmd-qnc

#opensource #analog #mixedsignal #rf #design

Compact MOSFET Mechanical Stress Model

Bonev, Nikolay, Dirk Michael Nuernbergk, and Christian Lang

Inclusion of Mechanical Stress Effects in a Compact MOSFET Model

Science and Technology 28, no. 2 (2025): 138-149.

DOI: 10.59277/ROMJIST.2025.2.02

<https://romjist.ro/full-texts/paper797.pdf>

1 Melexis Bulgaria EOOD, Sofia, Bulgaria
2 Melexis GmbH Erfurt, Erfurt, Germany

Abstract: The analog performance of integrated circuits relies on stable parameters of its transistors. Mechanical stress changes the electronic properties of silicon and, therefore, also the device parameters. For circuit design, a good model of these effects is needed for a predictable and reliable function of the circuits. This article extracts the changes of various MOSFET parameters under effect of mechanical stress. A compact description of the stress effects is derived by applying tensors of piezo coefficients. The deviations are included in the physically based compact EKV model. A comparison with measured data shows that the stress effects are modelled correctly within a 10 % error margin.

Fig: Extraction setup for the specific current Is

Technical Lecture - the Celebration of FET100

You are all invited to register and attend the Technical Talks being organized by 

IEEE Electron Device Society (EDS) Delhi Chapter – India and IEEE EDS Community Engagement Ad-hoc Committee 

along with The National Academy of Sciences, India-Delhi Chapter; 

Science Foundation Committee of Deen Dayal Upadhyaya College, University of Delhi, New Delhi, INDIA

Kindly register for each talk separately and forward the email to your students and other colleagues.

Technical Lecture on June 23, 2025 @ 03:00 pm Italy time (GMT +2) i.e. 06:30 pm India Time (GMT +5.30)

The Field Effect Transistor - Evolution of the Modeling Approaches - Massimo Rudan, Professor Emeritus, IEEE Life Fellow, Department DEI, University of Bologna, School of Engineering, Bologna, Italy

Registration Link to Join the Technical Talk on June 23, 2025 - https://events.teams.microsoft.com/event/ba686434-4454-4641-9781-455ae9a0b322@b51aeb7a-b8a2-4e7d-9a5c-be897389baf0

Technical Lecture on June 25, 2025 @ 12:00 pm Aachen, North Rhine-Westphalia, Germany (GMT +2) i.e. 03:30 pm India Time (GMT +5.30).

A Brief History of Device Simulation for MOSFETs - Christoph Jungemann, RWTH Aachen University

Registration Link to Join the Technical Talk on June 25, 2025 - https://events.teams.microsoft.com/event/2faa8109-5679-4ca2-b883-4255744d3859@b51aeb7a-b8a2-4e7d-9a5c-be897389baf0

Technical Lecture on June 27, 2025 @ 02:00 pm (GMT+2) Time in Stockholm, Sweden i.e. 05:30 pm (GMT + 5:30) Indian Standard Time

Efficient Semiconductor Devices for a Sustainable Future - Professor Mikael Östling, KTH Royal Institute of Technology, FIEEE, School of EECS, Stockholm, Sweden

Registration Link to Join the Technical Talk on June 27, 2025 - https://events.teams.microsoft.com/event/ade77f35-1fb9-4edf-8575-75fcbcbf3dc8@b51aeb7a-b8a2-4e7d-9a5c-be897389baf0

Technical Lecture on June 30, 2025 @ 04:30 pm CET (GMT+2) Time in Madrid, Spain which shall be 08:00 pm Indian Standard Time (GMT +05:30)

History, evolution and perspective of Thin Film Transistor technologies - Benjamin Iñiguez, Universitat Rovira i Virgili, Tarragona, Spain

Registration Link to Join the Technical Talk on June 30, 2025 -  https://events.teams.microsoft.com/event/4ae094a9-81c9-408c-8d34-60c307b9e66e@b51aeb7a-b8a2-4e7d-9a5c-be897389baf0

Technical Lecture on July 01, 2025 @ 09:00 am your time (GMT - 5) i.e. 07:30 PM Indian Standard Time (GMT +5:30)

Moore's Law and Radiation Effects on Microelectronics - Daniel M Fleetwood, Olin H. Landreth Professor of Engineering, Professor of Electrical and Computer Engineering, Professor of Physics, Vanderbilt University

Technical Lecture on July 01, 2025 @ 10:00 am (UTC - 5) i.e. 08:30 PM Indian Standard Time (GMT +5:30)
Perovskites – The New Frontier for Solar Photovoltaic Energy Conversion: Science and Technology - Vikram Dalal, Fellow: IEEE, APS, AAAS & Anson Marston Distinguished Professor, Iowa State University, USA

Registration Link to Join the Technical Talk on July 01, 2025 - https://events.teams.microsoft.com/event/65e9fd5e-4922-43be-88e2-1a039ca6bbd7@b51aeb7a-b8a2-4e7d-9a5c-be897389baf0

Technical Lecture on July 2, 2025 @ 4:00 pm Italy time (GMT +2) i.e. 07:30 PM Indian Standard Time (GMT +5:30)
Nanoelectronics and Nanosystems Device Engineering for Sustainability, in the Energy and Variability Efficiency(E.V.E.) Era - Simon Deleonibus, Life Fellow IEEE, Emeritus Fellow Electrochemical Society, Alternatives, Laboratoire d'Electronique et des Technologies de l'Information,(CEA-LETI), Grenoble, France.

Registration Link to Join the Technical Talk on July 02, 2025 - https://events.teams.microsoft.com/event/c2d9a858-4bed-4214-8ec2-d746a99a7a66@b51aeb7a-b8a2-4e7d-9a5c-be897389baf0

Technical Lecture on

July 3, 2025 @ 10:30 am Italy time (GMT - 4) i.e. 08:00 PM Indian Standard Time (GMT +5:30)
Spin-field effect transistor – the unusual FET - Supriyo Bandyopadhyay, Dept. of Electrical and Computer Engineering, Virginia Commonwealth University, Richmond, VA 23284

Registration Link to Join the Technical Talk on July 03, 2025 - https://events.teams.microsoft.com/event/dd41911d-528f-4c56-a6a3-7a0a9f43dcc1@b51aeb7a-b8a2-4e7d-9a5c-be897389baf0

-- with regards -- Manoj Saxena

EDS Community Engagement Ad Hoc Committee Chair
Chair-IEEE EDS Delhi Chapter (India) (2022 - )
FET Centennial (FET100) Ad Hoc Committee Member

Professor Manoj Saxena | आचार्य मनोज  सक्सेना 

FNASc(IN), FIETE(IN), SMIEEE(USA)

Department of Electronics | इलेक्ट्रॉनिक्स विभाग

Deen Dayal Upadhyaya College | दीन दयाल उपाध्याय कॉलेज

University of Delhi | दिल्ली विश्वविद्यालय

Dwarka Sector-3, New Delhi-110078 | द्वारका क्षेत्र -३, नई दिल्ली -११००७८

India | भारत

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[C4P] Micro Nano & Chips Tech 2025

 

Dear Colleagues, You are cordially invited to participate in  MICRO NANO & CHIPS TECH 2025 the 12th edition of the International Conference on Micro-Nanoelectronics, Nanotechnology and MEMS.  The event will take place at the Cultural Center of Chania in Crete, Greece, from November 6 to 9, 2025. Paper submissions are now open! For more information, please visit the conference website: https://2025.micro-nano.gr/

[mos-ak] [Media Note] MOS-AK INAOE Workshop, Puebla (MX)

MOS-AK INAOE Workshop on Semiconductor Technologies

Puebla (MX), May 14-16, 2025

Media Note

The MOS-AK Workshop on Semiconductor Technologies was held at the Instituto Nacional de Astrofísica, Óptica y Electrónica (INAOE) in Tonantzintla, Puebla, México, on May 14-16, 2025. This workshop was sponsored by MOS-AK, the INAOE, and IEEE through the Puebla Section and the local chapters for the Electron Devices and Instrumentation and Measurements societies. The MOS-AK event was inaugurated by Dr. Wladek Grabinski representing MOS-AK and IHP; Dr. David Sánchez, INAOE's General Director, Dr. Claudia Feregrino, Director of Research and Development for INAOE, and Dr. Roberto Murphy, the local organizer.

The objective of the workshop was to present the various open source tools for the design and simulation of integrated circuits (ICs). It consisted of in person as well as remote keynote speeches by experts in the field, and of a three-hour workshop on digital design synthesis.

The opening talk was by Dr. Wladek Grabinski (MOS-AK), covering a description of all the available FOSS CAD/EDA tools and programs for the design, simulation and fabrication of ICs using OpenPDK. This was a very enlightening run-through of the opportunities that can be exploited by all those who work in the field, at all levels. 

It was followed by a conference by Dr. Joaquín Faneca Ruedas, from the Centro Nacional de Microelectrónica (CNM) in Barcelona, Spain. He spoke about silicon nitride photonics, which is fast becoming a scalable platform for integrated optics. We then had the pleasure of listening to Dr. Medhi Saligane talk on agent AI for analog layout generation. Dr. Saligane is now with Brown University in the US. The first day was closed by a talk on memristor modeling by Dr. Arturo Sarmiento from INAOE. Memristors are fast becoming a common element in IC design, and their modeling and eventual characterization has become a very important field of endeavor in recent years.

The second day was opened by Dr. Colin Shaw from Silvaco (US) who gave a deep description of the status of the Si2 Compact Model Coalition.

The rest of the morning was dedicated to a three-hour workshop on digital circuit synthesis using open source CAD/EDA design tools.

Friday's first talk was by Dr. Harriet Parnell, a senior academic engineer at Ansys, and who gave a talk describing Ansys Lumerical FDTD tool, with a case study of a nanohole array. This was followed by a description of logic technology device innovations, given by Dr. Carlos Díaz, the Senior Director for Research and Development for Taiwan Semiconductor Manufacturing Company (TSMC). This great talk was followed by a presentation of the MOSbius project given by Dr. Peter Kinget, the Bernard J. Lechner Professor of Electrical Engineering at Columbia University. The workshop was closed by a researcher at INAOE, Dr. Reydezel Torres, who spoke of the simulation of chip-to-chip interconnects, another very important aspect of semiconductor technology.

The MOS-AK INAOE workshop was attended by 86 participants, mostly undergrad students but also by professional academicians and scientists. We can call it a success, and we hope that it has contributed to the country's much-needed progress in integrated circuit design and technology.

-- R.Murphy and W.Grabinski 

-- on the behalf of the MOS-AK INAOE Organizing Committee

---

Enabling Compact Modeling R&D Exchange

www.mos-ak.org

---

RM/WG120625

[mos-ak] [C4P] 9th Sino MOS-AK Workshop Shenzhen, August 14-16, 2025

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

9th Sino MOS-AK Workshop Shenzhen

August 14-16, 2025

Announcement and C4P

The International MOS-AK Workshop will be held on Aug. 14-16th, 2025 on- the beautiful campus of the Southern University of Science and Technology (SUSTech), Shenzhen, China. With the aggressive scaling of CMOS technologies and constantly emerging diversified devices, accurate device modeling technique poses severe challenge to circuit and system designers, in particular for RF/MW/mmW/THz/Power/optics. The workshop aims to strengthen a network and discussion forum for experts in the field, provide a forum for the presentation and discussion of the leading-edge research and development results of analytical modeling, compact modeling, characterization and simulation techniques for advanced devices, circuits and technologies. In addition to regular papers, MOS-AK Shenzhen 2025 will host three tutorial/workshop sessions on advanced GaN device modeling and circuit design, cryogenic CMOS modeling and circuit design, and millimeter-wave radar applications.   

Paper Submission: Authors from both academia and industry are invited to submit technical papers describing original work and/or advanced practices and R&D projects

LINK: https://music-lab.feishu.cn/share/base/form/shrcng2ont1UhjEF0YZlOX1kZHb

(any related enquiries can be sent to music@sustech.edu.cn)

Online Registration is open (any related enquiries can be sent to music@sustech.edu.cn)

Important Dates:

• Manuscript submission deadline: 30th June 2025
• Notification of Acceptance: 10th July 2025
• Submission of final manuscript: 15th July 2025
• MOS-AK Workshop:  Aug. 14-16th, 2025

-- Xiaoguang Liu, SUSTech and W.Grabinski for Extended MOS-AK Committee

WG110625

 

[mos-ak] [2nd Announcement] MOS-AK Workshop, London, July 11, 2025

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

MOS-AK Workshop, London, July 11, 2025

2nd Announcement and C4P

The Summer MOS-AK Workshop on Compact/SPICE Modeling will take place on July 11, 2025, at London Met. The Conference Centre, room TM3-03, 166-220 Holloway Road, London. This event is coorganized by London MET with the technical cosponsorship of UK IETE and IEEE EDS. We invite you to join us for MOS-AK workshop and learn from the experts in the field of Compact SPICE modeling, Verilog-A standardization and FOSS CAD/EDA IC design support for OpenPDKs.

Planned Summer MOS-AK Workshop at London MET is a forum to strengthen a network and discussion among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology manufacturers, circuit designers, and CAD/EDA tool developers and vendors supporting foundry/fabless interface strategies with the focus on OpenPDKs (eg: Skywater/GF CMOS, IHP RF BiCMOS) 

Important Dates:

• 2nd Announcement: June 2025
• Final Workshop Program: June 30, 2025
• MOS-AK Workshop: July 11, 2025

MOS-AK/London Speakers Tentative List (alphabetic order):

• Phillip-Ferreira Baade-Pedersen; IHP
• Mike Brinson; London MET
• Patryk Golec; Uni. Paris-Saclay
• Wladek Grabinski, MOS-AK/IHP
• Krzysztof Herman; IHP
• Rohith-Karnati Penchala; Pragmatic Semiconductor Ltd.
• Radu Sporea; Uni. Surrey
• Bal Virdee; London MET

Online Abstract Submission is open (any related enquiries can be sent to abstracts@mos-ak.org)

Online Free Registration is open (any related enquiries can be sent to registration@mos-ak.org)

W.Grabinski for Extended MOS-AK Committee

02062025

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[ICFOSS] Bridge Course for Eng/BSc Degree Aspirants

Bridge Course for Engineering/BSc Degree Aspirants - Season III

<https://icfoss.in/event-details/210>

ICFOSS is organizing a "Bridge Course" for Students who have completed their higher secondary education and aspires to pursue Engineering or BSc degrees in fields such as Computer Science, Electronics, Data Analytics, Physics, Mathematics and Statistics. The course will be conducted in two batches, scheduled from 26th to 31st May 2025 and 9th to 14th June 2025. This program mainly aims to provide them with the necessary knowledge, skills, and confidence to excel in various fields. It equips them with a strong foundation in Python programming and exposure to FOSS principles, setting them on a path for success and support during this transition period from school to college. This also aims to utilize this waiting period effectively by offering relevant educational activities and resources to help students to bridge the gap and stay engaged academically.

This is a combined course of Introduction to Python and Free and Open Source Software (FOSS), which is designed by ICFOSS to introduce students to Python programming and familiarize them with the concept and usage of free and open source software (FOSS). This program not only enhances their technical skills but also instills values of collaboration, knowledge sharing, and innovation that are essential in the field of technology. By the end of the course, students feels confident and well-prepared to tackle the challenges of college-level programming courses.

Objectives: Skill development and readiness for college- The course aims to develop essential skills required for success in college-level Engineering programs and BSc degrees in fields of Computer Science, Electronics, Data Analytics, Physics, Mathematics, and Statistics. It focuses on improving programming proficiency, logical reasoning, algorithmic thinking, and software development practices. The program also aims to support students, helping them stay motivated, engaged, and prepared for their upcoming BSc degrees or engineering programs.

Course Highlights: Live Classes, Structured curriculum by industry veterans, Customized for time flexibility, Custom learning path, Practical experience through simulations and project.

Mode of training: This training program is conducting in offline mode and our systematic approach includes skills assessment, intensive trainings and mentoring that helps valuable learning opportunities and unwavering support to students during this transition period.

Topics:

a) Introduction to Python : Introduction to Programming, Variables and Data Types, Control Flow and Decision Making, Lists, Tuples, and Dictionaries, Functions and Modules, File Handling, Object-Oriented Programming (OOP) Basics, Exception Handling, Deployment Using Flask, Working with External Libraries , Introduction to AI Concepts (Basics of AI, ML overview, Real-world Applications), Flask Project (Hands-on).

b) Free and Open Source Software: Introduction to FOSS, Linux Installation and Basics, Command-Line Basics, User and Group Management, Networking and Remote Access, System Services and Process Management, File System and Storage Management, Overview of FOSS Distros, Products, and Tools.

Target Audience: It is open to students who have completed their higher secondary education and aspires to pursue Engineering or BSc degrees in fields such as Computer Science, Electronics, Data Analytics, Physics, Mathematics, and Statistics.

Prerequisites: It is expected that students have a fundamental understanding of using computers.

Dates:

Name of Program	Dates	Time	Registration Fee
Batch 1	From 26th to 31st May 2025	10.00AM to 5.00 PM	Rs. 4,000/-
Batch 2	From 9th to 14th June 2025

Application Process: 

The number of participants is limited to 30 No.s per batch, on a first-come first-serve basis.

Course Duration: Total of 6 Days (6Hrs/Day)

Registration Fee: Rs. 4,000/-

Application deadline : 07th June 2025

For online payment, the bank accounts details of ICFOSS is provided below:

Account Name	ICFOSS
Account Number	67242303296
IFSC	SBIN0070737
Name of Bank	State Bank of India
Branch	Technopark, Thejaswini, Thiruvananthapuram

For Registration, follow: https://applications.icfoss.org/bridge-course-2025/
Please contact +91 7356610110 | +91 471 2413012 /13 /14 | +91 9400225962
between 10:00-17:00 hrs) for further clarifications.

EDS SCV/SF Hybrid DL Event on Friday June 27

IEEE SCV-SF EDS Distinguished Lecturer Event:

Friday, June 27th, 2025 – 11:30AM to 1PM (PDT)

Dr. Xing Zhou: Monolithic Co-integration of III-V Materials

into Foundry Si-CMOS in a Single Chip for Novel Integrated Circuits

The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter will host a hybrid Distinguished Lecturer event on June 27th at noon PST by Dr. Xing Zhou on the topic of "Monolithic Co-integration of III-V Materials into Foundry Si-CMOS in a Single Chip for Novel Integrated Circuits." The event will be held at Plug and Play Tech center in Sunnyvale, CA and also on zoom. The zoom meeting link will be sent to registered attendees a few days before the event. Event information below. The ticket options for both "In-person" and "On-line" attendance are available. Please select the appropriate ticket so we can get an accurate headcount for ordering food for the event.

Please register here: Link

Imran Bashir

SCV-SF EDS Chair

Distinguished Lecturer Event: Monolithic Co-integration of III-V Materials into Foundry Si-CMOS in a Single Chip for Novel Integrated Circuits

The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is hosting Dr. Xing Zhou.

When: Friday, June 27th, 2025 – 11:30AM to 1PM (PDT)

11:30AM - 12PM: Networking / Food

12PM-12:45PM: Lecture

12:45PM-12:55PM: Q&A

1PM Adjourn

Where: Rappi Room, Plug and Play Tech Center

440 N Wolfe Rd, Sunnyvale, CA 94085

This is an hybrid event and attendees can participate via Zoom. The Zoom meeting link will be sent a few days before the event to registered attendees.

Contact: ieeescveds at gmail.com

Speaker: Dr. Xing Zhou

Abstract: As Moore's Law is slowing down and eventually approaching an end for conventional CMOS, new platforms for producing circuit-level innovation are desired. At the same time, it is not desirable to throw away the existing Si-CMOS infrastructure to start new. This talk presents an overview of the 10-year research program, which is a "vertical" innovative platform by "inserting" III-V layers into a conventional Si-CMOS foundry process. The talk also presents a unified compact model for generic GaN/InGaAs-based HEMTs in the context of the hybrid III-V + CMOS technology developed for future heterogeneous integrated circuits. The developed model has been implemented in a hybrid III-V/CMOS foundry PDK for designing heterogeneous circuits in III-V/Si monolithically co-integrated technology.

Speaker Bio: Dr. Xing Zhou obtained his B.E. degree in electrical engineering from Tsinghua University in 1983, M.S. and Ph.D. degrees in electrical engineering from the University of Rochester in 1987 and 1990, respectively. He has been with the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore from 1992 to 2024. His past research interests include Monte Carlo simulation of photocarrier transport and ultrafast phenomena as well as mixed-mode circuit simulation and CAD tool development. His research at NTU mainly focuses on nanoscale CMOS compact model development. His research group has been developing a unified core model for nanoscale bulk, SOI, double-gate, nanowire CMOS, as well as III-V HEMTs. He has given more than 150 IEEE EDS distinguished lectures and invited talks at various universities as well as industry and research institutions. Dr. Zhou was the founding chair for the Workshop on Compact Modeling (WCM) in association with the NSTI Nanotechnology Conference (2002–2018). He was an editor for the IEEE Electron Device Letters (2007–2016), a guest Editor-in-Chief for the special issue of the IEEE Transactions on Electron Devices (Feb. 2014) on compact modeling of emerging devices, and a member of the Modeling & Simulation subcommittee for IEDM (2016, 2017). He was an Elected Member-at-Large of EDS Board of Governors (2004–2009; 2011–2016) and served as Vice-President for Regions/Chapters (2013–2015). He has been an EDS Distinguished Lecturer since 2000. He is a Life Senior Member of the IEEE and currently serves as chair for the RS/EPS/EDS Singapore Joint Chapter.