Oct 8, 2025

[mos-ak] [Special Issue] 7th International Sino MOS-AK Workshop


Special Issue on the 7th International Sino MOS-AK Workshop
Jun Zhang, Wladek Grabinski, Yuehang Xu (editors)
Int JNM, 38: e70114.
First published: 07 September 2025
1. College of Integrated Circuit Science and Engineering, Nanjing University, Jiangsu (CN)
2. MOS-AK and GMC Consulting (CH)
3. School of Electronic Science and Engineering, Uni. Chengdu, Sichuan (CN)

As device structures become increasingly complex, with the continuous emergence of novel materials, unconventional architectures, and new physical phenomena, the coupling of multiple physical domains, including thermal, electrical, and optical effects, is becoming ever more prevalent. At the same time, rising development and manufacturing costs place additional demands on modelers to deliver representations that are both accurate and computationally efficient across the entire chain from device physics to circuit behavior. Modeling serves two complementary purposes: Theoretical models provide insight into the operating principles of devices, while also guiding design optimization and enabling engineers to fully exploit intertwined physical effects. Analytical modeling, however, often requires careful trade-offs among accuracy, generality, and simplicity. Models must be predictive enough to inform design while offering meaningful physical insight. In modern semiconductor devices, which often feature three-dimensional geometries, solving the coupled semiconductor physics equations analytically is extremely challenging or even impossible. Closed-form solutions are typically unattainable, so judicious simplifications are necessary to ensure that models remain tractable and practically useful.

The papers in this Special Issue address these challenges by balancing physical fidelity with computational efficiency. They deepen our understanding of device physics while providing models that are both insightful and practical, with applications spanning cryogenic electronics, wide-bandgap devices, and radiation-hardened systems.

Su et al. present a charge-based analytical model for bulk MOSFETs, that is, valid down to 10 mK. Their work clarifies the interface-trap-dominated mechanisms that lead to threshold voltage divergence between NMOS and PMOS devices and quantifies significant analog parameter enhancements, including a 73% increase in PMOS cutoff frequency at 4 K. These findings are essential for quantum-control electronics. Complementing this, Mao et al. provide a comprehensive review of four physics-based compact models for GaN HEMTs, namely MVSG, ASM HEMT, EPFL, and QPZD. They analyze how each model addresses challenges such as trapping effects, self-heating, and process variability, and highlight emerging opportunities for combining physical models with machine learning to accelerate parameter extraction and quantify uncertainties. In the area of radiation-tolerant electronics, Xu et al. introduce a machine-learning approach using an ant-colony-optimized neural network. By adaptively sampling critical waveform regions, their method achieves an RMS error of only 0.82% in predicting single-event transient currents, surpassing the fidelity limits of traditional double-exponential pulse models and enabling high-precision radiation effect simulation for aerospace applications. Meanwhile, Deng et al. demonstrate a practical strategy for AI-assisted SPICE integration. They employ geometry-parameterized scaling laws for spiral inductors and machine-augmented Power MOS trans-conductance models to accelerate parameter extraction by an order of magnitude while preserving full SPICE compatibility. This approach significantly streamlines industrial design workflows.

Collectively, these contributions point to a trend toward physics-informed, data-driven co-design methodologies. By combining rigorous physical insight with computationally efficient, machine learning–aware workflows, they enable robust optimization of devices and circuits across a wide range of applications, from quantum interfaces to aerospace systems.

Future research should prioritize the development of standardized interfaces between AI tools and physical models, the extension of models to three-dimensional integrated wide-bandgap architectures, and the establishment of co-design frameworks for emerging ultra wide–bandgap materials capable of operating in environments ranging from near-zero Kelvin to orbital radiation conditions. We sincerely thank all authors for their outstanding contributions, which have advanced the frontier of semiconductor modeling science.

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Oct 5, 2025

[Deadline] extended to Oct.15 2026


10th IEEE Electron Devices Technology and Manufacturing
(EDTM 2026) Conference
https://ieee-edtm.org/
March 1-4, 2026 Penang, Malaysia 

EDTM2026 paper submission date has been extended to 15th October 2025

Submit your papers today in any of the 13 tracks and see you in Penang, Malaysia from 1st - 4th March 2026.




Oct 4, 2025

[workshop] Advances in Semiconductor and Emerging Devices for Chip Design

5-Day Online International Workshop on
Recent Advances in Semiconductor and Emerging Devices for Chip Design
Oct. 6-10, 2025
Organized by the Department of Electronics, Dhanamanjuri University (DMU), Manipur,
in Collaboration with IEEE Silchar Subsection

Upcoming 5-Day International Workshop on “Recent Advances in Semiconductor and Emerging Devices for Chip Design” (6–10 October 2025) organized by Dhanamanjuri University (DMU) Manipur, in collaboration with IEEE Silchar Section. This unique event, led by Dr. Khoirom Johnson Singh, Ph.D. and his dedicated team, brings together global experts from India, Europe, and beyond. Register Online

With speakers covering topics from GaN devices and memristors to cryogenic CMOS, nanosheet FETs, biomedical circuits, and spintronics for novel computing, this workshop will serve as a melting pot of ideas, a platform for young researchers and students to learn, question, and seed new collaborations.






















Education equips young minds with the foundations of knowledge, preparing them to understand technological advancements and their role in shaping society. Yet, in research, knowledge alone is not enough. To truly innovate, we must disseminate our work, engage with peers, and foster collaborations across disciplines and borders. This is where the seeds of research truly take root and grow.

Collaboration is more than sharing data or co-authoring papers. It is about bringing together diverse perspectives, connecting physics with engineering, theory with experimentation, and academia with industry. Interdisciplinary approaches not only accelerate breakthroughs, but also open new directions that no single researcher could achieve alone.





[paper] Is there anything left to do in TCAD?

Z. Stanojevic, F. Schanovsky, G. Rzepa, X. Klemenschits, H. Demel, 
O. Baumgartner, C. Kernstock, and M. Karner
Is there anything left to do in TCAD?
SISPAD  in Grenoble, Sept. 24 2025
https://sispad2025.inviteo.fr/

1. Global TCAD Solutions GmbH., Bosendorferstraße 1/12, 1010 Vienna (A) 

Abstract: Over the past decade, the development of commercial technology computer-aided design (TCAD) software has followed an evolutionary rather than revolutionary path. Alongside established continuum and particle-based approaches in both process and device simulation, advanced carrier transport models - such as deterministic bulk and subband Boltzmann transport equation (BTE) solvers and non-equilibrium Green’s functions (NEGF) - have been incorporated into the TCAD toolkit for single-device simulation. At the system level, the field of design-technology co-optimization (DTCO) has expanded to encompass variability, reliability, and the extension of TCAD methodologies from devices to circuits. However, most of these innovations were introduced over a decade ago, prompting the question: What remains to be developed in TCAD? We address this question by analyzing current limitations and potential future directions in TCAD development across three key dimensions: (1) fidelity, (2) integration, and (3) efficiency - each with particular relevance in commercial and industrial contexts. We examine ongoing challenges in classical TCAD, advanced transport modeling, and DTCO flows, and point to potential directions for future developments. Among these, we include various methodologies related to machine learning and hardware accelerators, particularly within the efficiency dimension.


FIG: Device 3D structure generated from a layout (GDSII) and a technology file

See also...

Oct 3, 2025

[paper] THz MOST based on aligned carbon nanotube arrays

Jianshuo Zhou, Zipeng Pan, Li Ding, Lin Xu, Xiaohan Cheng, Haitao Li, Fenfa Yao, Chuanhong Jin, Maguang Zhu, Lijun Liu, Huiwen Shi, Zhiyong Zhang and Lian-Mao Peng
Terahertz metal–oxide–semiconductor transistors based on aligned carbon nanotube arrays. 
Nat Electron (2025)
DOI: https://doi.org/10.1038/s41928-025-01463-6

1. Key Laboratory for the Physics and Chemistry of Nanodevices and Center for Carbon-based Electronics, Peking University
2. Hunan Institute of Advanced Sensing and Information Technology, Xiangtan University, Xiangtan, China
3. Chongqing Institute of Carbon-based Integrated Circuits, Peking University, Chongqing, China
4. Academy for Advanced Interdisciplinary Studies, Peking University, Beijing, China
5. State Key Laboratory of Silicon and Advanced Semiconductor Materials, Zhejiang University, Hangzhou, China
6. Frontiers Science Center for Nano-optoelectronics, Peking University, Beijing, China


Abstract: Films of aligned semiconducting carbon nanotubes could be used to build complementary metal–oxide–semiconductor field-effect transistors for digital integrated circuits and radio-frequency transistors for terahertz analogue integrated circuits. However, the operating frequencies of such devices remains too low for potential application in the sixth generation of wireless communications. Here we report metal–oxide–semiconductor field-effect transistors that are based on aligned carbon nanotube films and have a cut-off frequency beyond 1 THz. By optimizing gate structures and fabrication processes, we create devices with a gate length of 80 nm that have a carrier mobility of over 3,000 cm2 V−1 s−1, as well as an on-state current of 3.02 mA µm−1, a peak transconductance of 1.71 mS μm−1 at a bias of −1 V, and a saturation velocity of 3.5 × 107 cm s−1. By introducing a Y-shaped gate, we also create devices with gate lengths of 35 nm that have an extrinsic cut-off frequency (fT) of up to 551 GHz and a maximum oscillation frequency (fmax) of 1,024 GHz. Finally, we use devices with a gate length of 50 nm to fabricate mmWave-band (30 GHz) radio-frequency amplifiers that have a gain of up to 21.4 dB.

Fig: Characteristics of Y-gate structure in A-CNT MOSFETs.

Acknowledgements: This work is supported by the National Key Research & Development Program (grant number 2022YFB4401603 to L.D.) and Natural Science Foundation of China (grant numbers 62171004 to L.D., 92477201 to L.-M.P. and 62225101 to Z.Z.).

Sep 29, 2025

[Thesis] Verilog-A MOSFET Model for Analog IC Design

Master Thesis by Alba Gallego Velázquez
Defended: July 1, 2025
Technical University of Crete, Chania
Tutor: Prof. Matthias Bucher

Abstract: The present thesis sets out the development and implementation of a compact model of a MOSFET, based on the theoretical EKV model, and implemented using the Verilog-A language. The utilization of simulation and compilation environments, such as the open server OpenVAF and Ngspice, is instrumental in facilitating the effective execution of the work. The construction of a model that can perform the function of an nMOS or a pMOS nanometric operating in a saturated state is facilitated by these. In this model, physical dependencies and second-order effects are incorporated, ensuring the attainment of continuous expressions for all inversion regions. The model's behavior is validated against experimental data by means of simulation. This results in an accurate, compact and versatile model, which is suitable for supporting integrated analog circuits designs with a wide range of values for the inversion coefficient.
Fig: Normalized (𝐺𝑚𝑠 ·𝑈𝑡)/ID of the nMOS vs. the inversion coefficient (IC)




[paper] Gate stack engineering of 2D transistors

Yeon Ho Kim, Donghun Lee, Woong Huh, Jaeho Lee, Donghyun Lee, 
Gunuk Wang, Jaehyun Park, Daewon Ha and Chul-Ho Lee*
Gate stack engineering of two-dimensional transistors.
Nat Electron 8, 770–783 (2025)
DOI: 10.1038/s41928-025-01448-5

* Laboratory of Emerging Electronics & optoElectronics, SNU / julianus95@snu.ac.kr

Abstract: Gate stack engineering has helped enable aggressive device scaling in silicon complementary metal–oxide–semiconductor technology. Two-dimensional (2D) materials are a potential replacement for silicon in next-generation electronics. However, creating gate stacks that are capable of effective and reliable channel control with such materials is inherently challenging owing to the lack of compatible dielectrics and fabrication methods. Here we explore the development of gate stack engineering technologies for two-dimensional transistors. We benchmark key performance metrics for two-dimensional metal–oxide–semiconductor gate stacks against current silicon-based technologies, as well as the targets set by the International Roadmap for Devices and Systems. We also highlight recent advances in ferroelectric-embedded gate stacks, which offer additional functionalities and could be of use in the development of high-speed non-volatile memories and logic-in-memory devices, as well as low-power transistors. Finally, we consider the technical challenges that need to be addressed to develop advanced electronic technologies based on two-dimensional transistors.
FIG: CMOS logic technology roadmap and potential of angstrom-scale 2D transistors

Acknowledgment: This research was supported by the Ministry of Science and ICT under the Next-Generation Intelligent Semiconductor Technology Development Project and the Nano and Material Technology Development Program (Future Technology Labs). The graduate researchers received additional support from BK21 Four and the SNU Graduate School of AI Semiconductor.


Sep 13, 2025

[Online Publications] 22nd MOS-AK/ESSERC Workshop in Munich (D) on Sept. 8 2025



Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
MOS-AK/ESSERC Workshop
Munich, Sept.8, 2025

The consecutive, 22nd MOS-AK Workshop has been organized as an integral part of 51st ESSERC in Munich (D) on Sept. 8 2025. The MOS-AK workshop publications [1-6], with individually assigned DOI numbers, are available online at:

The development of open-source Process Design Kits (PDKs) is crucial for democratizing access to advanced semiconductor technologies. IHP's OpenPDK initiative bridges the gap between academia, startups, and the semiconductor industry by offering a fully open and manufacturable SG13G2 BiCMOS OpenPDK for analog/RF, mixed-signal, and digital IC applications. Aligning with the EU Chips Act, this initiative emphasizes open collaboration to overcome economic and technical barriers in semiconductor innovation. The workshop introduces SG13G2 OpenPDK and Free and Open-Source Software (FOSS) tools for IC designs, including Verilog-A devices, schematic capture, SPICE simulation, layout, physical verification in advanced design flow up to final typeout.

To learn more about IHP OpenPDK Initiative and its Certified Design Courses, visit online depositories as listed below:

Open-Source Digital Design Course: https://github.com/OS-EDA/Course
  • Full RTL-to-GDSII workflow using OpenROAD and SG13G2 PDK
  • Feedback integrated via GitHub & live sessions
  • Trial run Feb 2025: 15 on-site participants selected from 85+ applicants
Open-Source Analog Design Course: https://github.com/IHP-GmbH/IHP-AnalogAcademy
  • Hands-on design with SG13G2 PDK; Strong emphasis on analog/RF practice, focused on the layout and verification, including process variation analysis of analog/RF ICs
  • Explored designs: Bandgap, 50 GHz PA, SAR ADC
  • Tools: Ngspice, Xyce, Xschem, Qucs, Klayout
  • Trial run June 2025: with 16 on-site participants selected from 80+ applicants
MOS-AK Workshop References:

[1] M. Yazici and R. Scholz, "IHP OpenPDK Roadmap", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113282.


[2] Árpád Bűrmen, "The OpenVAF Verilog-A Compilerfor the OpenPDK Ecosystem", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113774.


[3] M. Volker, "User-friendly FDTD EM Workflow for IHP OpenPDK with Automatic Meshing", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113926.


[4] Mike Brinson, "Building Component Libraries for Use with the IHP OpenPDK and FOSS Tools", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113932.

[5] Mirjana Videnović-Mišić, "Analog IC Flow Automatization", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113935.

[6] Ralph Steiner Vanha, "MOS SizingTool – A Single Transistor Simulator", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113946.

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Sep 12, 2025

[paper] MicroLEDs SPICE Model

Sultan El Badaoui1,2, Patrick Le Maitre1, Anthony Cibié1, Julia Simon1, Aurélien Lardeau-Falcy1, 
Jeremy Bilde1, Louwenn Cherruault1, Manon Arch1, Michael Pelissier1, Yannis Le Guennec2
SPICE Modeling of GaN MicroLEDs for Optical Communication
Journal of the Society for Information Display, 2025; 0:1–16
DOI 10.1002/jsid.2105

1 Univ. Grenoble Alpes, CEA LETI, Minatec, Grenoble (F)
2 Univ. Grenoble Alpes, CNRS, Grenoble-INP, GIPSA-lab, Grenoble (F)

Abstract: With the rapid expansion of data centers, there is a growing demand for high data-rate, energy-efficient optical links over short distances. One potential technology for this application is Gallium-Nitride (GaN) based microlight emitting diodes (μLEDs), thanks to their compact size, high-speed operation, and ease of manufacturability. During the development of these μLEDs, modeling plays an essential role in optimizing their performance. In this paper, we present various models to estimate both the static and dynamic performance of GaN μLEDs of various sizes. We then propose a methodology to integrate these models into a unified equivalent circuit model, enabling the simulation of the full response of the μLED. Finally, we implement this unified model in a circuit-simulation-compatible module and replicate the experimental setups within a simulation software to evaluate the module's ability to accurately simulate the μLED's response.



FIG: (a) SEM image of a 50-μm μLED, showing the GSG pad configuration and the grid contact over the μLED
(b) Schematic of the stack of the μLEDs 
9c) Simulation setup used to for transient simulation

Acknowledgments: This work is part of the IPCEI Microelectronics and Connectivity and was supported by the French Public Authorities within the frame of France 2030 and by the Institut Carnot CEA-Leti.

Sep 5, 2025

[Conference] 33rd Austrochip 2025

September 25, 2025 – Linz, Austria

The TT workshop program


08:00 – 09:00 Coffee & Registration
09:00 – 09:15 Conference Opening
09:15 – 10:00 First Keynote-Address

  • IHP OpenPDK and MPW: Pushing Open-Source EDA tools to Analog and RF Design René Scholz IHP – Leibniz Institute for high performance Microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany

10:00 – 10:45 Second Keynote-Address
  • Open-source SoC design using PULP Frank K. Gürkaynak ETH Zürich, IIS, ETZ J 60.1, Gloriastrasse 35, 8092 Zürich, Switzerland
10:45 – 11:00 Break
11:00 – 12:00 Paper Session I:
Session Chair: TBA, TBA
  • Gain Expansion Generator based on a Reduced Conduction Angle for H-Band Applications Thomas Ufschlag, Benjamin Schoch, Lukas Gebert, Dominik Wrana, Axel Tessmann and Ingmar Kallfass University of Stuttgart (ILH), Fraunhofer Institute for Applied Solid State Physics IAF
  • Greyhound: A Reconfigurable and Extensible RISC-V SoC and eFPGA on IHP SG13G2 Leo Moser, Meinhard Kissich, Tobias Scheipel and Marcel Baunach Graz University of Technology
  • Comparison of Low Power Digitally Controlled Ring Oscillator Architectures in 12 nm FinFET Florian Schneider, Luca Avallone and Alicja Michalowska-Forsyth Infineon Technologies Austria AG Institute of Electronics (IFE), Graz University of Technology
12:00 – 12:30 Poster & Sponsor Pitch Session
12:30 – 14:00 Lunch
14:00 – 15:15 Paper Session II:
Session Chair: TBA, TBA
  • A 150-GHz 9-dBm EIRP Open-Source FMCW Radar Chip in 130-nm BiCMOS Ghaith Al Sabagh, Georg Zachl and Harald Pretl Institute for Integrated Circuits and Quantum Computing, JKU Linz

  • A CMOS Source-Coupled Relaxation Oscillator Achieving Close-in Phase Noise of −72.9 dBc/Hz at a 1 kHz Offset Baset Mesgari, Saeed Saeedi, Reinhard Feger and Horst Zimmermann Institute for Communications Engineering and RF-Systems, Johannes Kepler University Linz Faculty of Electrical and Computer Engineering, Tarbiat Modares University Christian Doppler Laboratory MWTH

  • A FR3, 25 dBm Unbalanced MMIC GaAs Doherty Power Amplifier with Auxiliary Gate Voltage Modulation for Linearity Improvement Abdolhamid Noori, Fatemeh Abbassi, Christoph Wagner, Christian Fager and Gregor Lasser Chalmers University of Technology, Silicon Austria Labs

  • A 72.7-90.4 GHz VCO with a Stacked NMOS based Tuning Network in 28nm FDSOI Waseem Abbas, Samir Aziri and Christoph Wagner Silicon Austria Labs

  • A D-Band Active Down-Conversion Mixer with 80 GHz IF for FMCW Radar Frequency Extension Fatemeh Abbassi, Samir Aziri, Waseem Abbas, Christoph Wagner and Timm Ostermann Silicon Austria Labs, Institute for Integrated Circuits and Quantum Computing, JKU Linz

15:15 – 15:30 Break
15:30 – 16:45 Paper Session III:
Session Chair: TBA, TBA
  • Design Automation of a Digitally Controlled Ring Oscillator using CUAS Cell Creator Framework Daniel Cerdà Holmager, Santiago Martin Sondón, Violeta Petrescu, Wolfgang Scherr and Johannes Sturm Carinthia University of Applied Sciences in Austria, CUAS
  • Event-Based ADCs vs. Nyquist ADCs: Rethinking Performance Metrics Simon Dorrer, Anna Werzi, Bernhard A. Moser, Michael Lunglmayr and Harald Pretl Institute for Integrated Circuits and Quantum Computing, JKU Linz Institute of Signal Processing, JKU Linz
  • Modeling Location-dependent Random Telegraph Noise for Circuit Simulators Florian Berger, Gerhard Landauer, Alicja Michalowska-Forsyth, Martin Flatscher, Philipp Greiner and Stefan Gansinger Institute for Electronics, Graz University of Technology Power and Sensor Systems, Infineon Technologies
  • An 8.1-µW 12-bit Non-Binary Self-Clocked SAR-ADC in 130 nm Open-Source PDK Ali Olyanasab, Patrick Fath, Leonhard Schreiner, Christoph Guger and Harald Pretl g.tec medical engineering GmbH Institute for Integrated Circuits and Quantum Computing, JKU Linz
  • SPAD Active Quenching/Resetting Circuit in 0.35-µm HV-CMOS Enabling 24V Excess Bias for PDP >90% Sherwin Nasirifar, Baset Mesgari, Christoph Ribisch, Saman Kohneh Poushi and Horst Zimmermann Institute of Electrodynamics, Microwave and Circuit Engineering, TU Wien Institute for Communications Engineering and RF Systems, JKU Linz Austrian Institute of Technology (AIT), Vienna Silicon Austria Labs

16:45 – 17:00 Conference Closing, Best Paper Award & Outlook Austrochip 2026

Sep 3, 2025

Aging Model for ASAP 7nm Predictive PDK

Neha Gupta1, Lomash Chandra Acharya1, Mahipal Dargupally1, Khoirom Johnson Singh2, Amit Kumar Behera1, Johan Euphrosine3, Sudeb Dasgupta1, Anand Bulusu1
Aging Model Development for ASAP 7 nm Predictive PDK: Application in Aging-Aware Performance Prediction of Digital Logic and ADCs in Data Acquisition System
IEEE ISVLSI (2025)
DOI: 10.1109/ISVLSI65124.2025.11130265
1 Indian Institute of Technology, Roorkee, (IN)
2 Dhanamanjuri University, Manipur (IN)
3 Google, Tokyo (J)


Abstract: As semiconductor technology advances to sub- 10nm nodes, Design Technology Co-Optimization (DTCO) has emerged as an essential paradigm for co-optimizing processes and design methodologies. Although the ASAP 7nm Predictive PDK (Process Design Kit), which is a free and open-source academic PDK developed by the Arizona State University (ASU) research team, is a useful open-source platform for digital design research, it lacks key DTCO features such as reliability modeling, aging resilience, and security-aware co-design. In this article, we present our developed aging model for ASAP 7nm Predictive PDK and utilize it to evaluate the impact of transistor aging on the performance of digital timing logic and a memory cell which provides timing feedback from a DTCO point-of-view concerning standard cells and other reference circuit designing. In this work, different logic gates, benchmark circuits, N-stage ring oscillator and 6T SRAM bitcell are used as the representative of digital logic and memory cell, respectively. We further utilize our developed aging model to predict performance of an analog-to-digital converter in data acquisition systems. The developed aging model would be released for the research community for further improvement in design reliability and technology enhancement along with OPENROAD Tool flow.

Fig. (a) Flow chart for representing steps required to develop Verilog-A aging model 
for ASAP 7nm Predictive PDK (FinFET) process. 
(b) Inclusion of the developed aging model to incorporate aging impact in static timing analysis (STA).

Sep 1, 2025

FOSSEE eSim Marathon – Circuit Design & Simulation with IHP SG13G2

Design, Simulate, Showcase
Unlock Open-Source VLSI Design  using eSim + IHP SG13G2 OpenPDK!!!

The eSim Marathon - Circuit Design & Simulation with IHP SG13G2 is a nationwide circuit design competition where participants use eSim, an open-source EDA tool developed by FOSSEE, IIT Bombay, to design and simulate circuits using the IHP OpenPDK for 130nm SG13G2 BiCMOS technology from IHP Microelectronics, Germany.

Key Highlights:
  • Tool Used: eSim - a free and open-source alternative to commercial circuit design tools 
  • OpenPDK Used: IHP SG13G2 - enables design of analog, digital, and RF circuits at 130 nm BiCMOS.
  • Objective: Design, simulate, and submit functional analog/digital/mixed-signal circuits.
  • Eligibility: Open to individuals - students, hobbyists, and early-career professionals.
  • Learning Outcomes: Participants gain hands-on VLSI design experience using a real foundry OpenPDK, develop schematics, run simulations, and build documentation - entirely with open tools.

Timeline

Date Activity Description
1 Sept. - 15 Sept. 2025 Registration for the Marathon Complete the participation form
16 Sept. 2025 Marathon Inauguration Webinar FOSSEE Team will introduce through eSim, IHP and Marathon process
16 Sept. - 23 Sept. 2025 Literature Survey Participants need to research the topic available in papers/journals on the web
23 Sept. 2025 Report Submission Submit one-page research conclusion and circuit implementation plan
23 Sept. - 5 Oct. 2025 Implementation Design, characterise and simulate using eSim platform
5 Oct. - 8 Oct. 2025 Report Submission & Documentation Upload reference and actual circuit/waveform using eSim
25 Oct. 2025 Result Declaration (Provisional) Announcement of provisional results



Aug 28, 2025

[paper] Human Language to Analog Layout

Ali Hammoud, Chetanya Goyal, Sakib Pathen, Arlene Dai, Anhang Li, Gregory Kielian,
and Mehdi Saligane
Human Language to Analog Layout Using GLayout Layout Automation Framework
ACM/IEEE MLCAD 

Abstract: Current approaches to Analog Layout Automation apply ML techniques such as Graph Convolutional Neural Networks (GCN) to translate netlist to layout. While these ML approaches have proven to be effective, they lack the powerful reasoning capabilities, an intuitive human interface, and standard evaluation benchmarks that have been improving at a rapid development pace in Large Language Models (LLMs). The GLayout framework introduced in this work translates analog layout into an expressive, technology generic, compact text representation. Then, an LLM is taught to understand analog layout through fine-tuning and in-context learning using Retrieval Augmented Generation (RAG). The LLM is able to successfully layout unseen circuits based on new information provided in-context. We train 3.8, 7, and 22 Billion parameter quantized LLMs on a dataset of less than 50 unique circuits, and text documents providing layout knowledge. The 22B parameter model is tuned in 2 hours on a single NVIDIA A100 GPU. The open-source evaluation set is proposed as an automation benchmark for LLM layout automation tasks, and ranges from 2-transistor circuits to aΔΣ ADC. The 22B model completes 70% of the tasks in the evaluation set, and passes DRC and LVS verification on 44% of evaluations with verified correct blocks up to 4 transistors in size.

FIG: Full process of translating user prompt to a final layout.

Acknowledgments: The authors would like to thank the open-source community for their support.
 

[paper] Differential Aging-Aware Static Timing Analysis

Lomash Chandra Acharya, Neha Gupta, Khoirom Johnson Singh, Mahipal Dargupally, Neeraj Mishra, 
Arvind Kumar Sharma, Ajoy Mondal, Venkatraman Ramakrishnan, 
Sudeb Dasgupta, and Anand Bulusu
DAAS: Differential Aging-Aware STA for Precise Timing Closure With Reduced Design Margin
in IEEE Transactions on Device and Materials Reliability
DOI: 10.1109/TDMR.2025.3603098

1.) Department of Electronics and Communication Engineering, IIT Roorkee (IN)
2.) Department of Electronics, Dhanamanjuri University, Imphal (IN)
3.) Department of Electronics and Electrical Engineering, BITS Pilani (IN)
4.) Semiconductor Technology and Systems Department, IMEC (B)
5.) EDA Group, Texas Instruments, Bengaluru (IN)
6.) OnSemi Technology, Bengaluru (IN)


Abstract : This article introduces DAAS, a Differential Aging-Aware Static Timing Analysis methodology built upon an Effective Current Source Model (ECSM). The primary objective is to achieve precise timing closure for digital integrated circuits while minimizing design margins. To achieve this goal, we employ a one-time aging simulation using a single MOS device-based approach. This approach estimates the change in threshold voltage (Vth) denoted by (Vth) in a MOS device under diverse operating conditions, such as supply voltage and temperature, in the presence of aging. The estimated value of (Vth) is then used to update the model coefficient of timing models for various combinational gates. These updated models are utilized to generate differential aging-aware standard cell library data in an industry-standard Liberty format. This data can be seamlessly integrated into common STA environments like Synopsys PrimeTime, facilitating the estimation of timing closure for designs with different blocks operating at varying voltages and temperature conditions. The proposed methodology eradicates the need for circuit-level aging simulation to generate differential aging-aware standard cell library data. It demonstrates an average error of 2.5% compared to conventional aging simulation on standard cells using the STMicroelectronics (STM) 28nm CMOS process. Furthermore, the method significantly reduces the required number of SPICE/aging simulations by approximately 99.984% to generate differential aging-aware standard cell library characterization data. Further, we demonstrate the versatility of the proposed DAAS methodology for the generation of standard cell library data in the case of PDK migration and different device variants without performing full SPICE-level simulations.

FIG: Representation of the approach used to model a standard cell 
with transistor topology of a buffer and its terminal transitions as a test case.

Aug 25, 2025

[Education Corner] Tinkering with CMOS Circuits

P. Kinget
Tinkering with CMOS Circuits at the Lunch Table with MOSbius
[Education Corner]
in IEEE Solid-State Circuits Magazine, vol. 17, no. 3, pp. 72-78, Summer 2025
doi: 10.1109/MSSC.2025.3583537

Abstract: Experimental validation is a critical step in any engineering discipline and doing lab experiments is an essential part of the formation of an engineer. Creating relevant experiments to train integrated-circuit designers has become difficult due to the lack of appropriate components. We designed the MOSbius chip and adapter PCB so learners can perform circuit labs with MOS transistor topologies that are relevant to modern transistor-level IC design. With MOSbius, students can experiment with customized CMOS circuits early on – without the challenges, delays, and cost of designing a custom integrated circuit. Yet, MOSbius serves as a great steppingstone towards full custom IC design courses.

Fig: An overview of the MOSbius platform. Students design and realize transistor-level MOS circuits
using on-chip-style topologies and evaluate them experimentally.

Acknowledgment: Many thanks to the MOSbius crew of enthusiastic current and former students: Longyi Li, Yunfan Gao, Zhuo Chen, Petar Barac, Ray Xu, Hongzhe Jiang, Cade Gleekel, Nico de la Cruz, Rosnel Alejandro Leyva-Cortes, Yuechen He, Jingde Hu, Qizhe Wu, Jingrui Li, Xianglin Pu, Yuntao Guo, and Andrew Chon. Thanks to Apple, Inc. for fabrication funding through the Columbia ELEN E6350 VLSI Design Lab course. Thanks to Yannis Tsividis (Columbia), John Pigott (NXP), Babak Soltanian (Tayen.Ai), Jianxun Zhu (Analog Devices, Inc.), Jared Zerbe (Apple), Eric Smith (Apple), Doug Mercer (ADI), and many others for engaging discussions and sharing of ideas.

Aug 21, 2025

[paper] Geometrical variability in FinFETs

C. Medina-Bailon, J.L. Padilla, L. Donetti, C. Navarro, C. Sampedro, F. Gamiz,
Geometrical variability impact on the gate tunneling leakage mechanisms in FinFETs,
Solid-State Electronics, 2025, 109212,
ISSN 0038-1101,
DOI: 10.1016/j.sse.2025.109212.

Abstract: Given the critical role that quantum tunneling effects play in the behavior of nanoelectronic devices, it is essential to investigate the influence and restraints of these phenomena on the overall transistor performance. In this work, a previously developed gate leakage model, incorporated into an in-house 2D Multi-Subband Ensemble Monte Carlo simulation framework, is employed to analyze the leakage current flowing across the gate insulator. The primary objective is to evaluate how variations in key geometrical parameters (specifically, gate oxide and semiconductor thicknesses dimensions) affect the magnitude and bias dependence of tunneling-induced leakage. Simulations are performed on a representative FinFET structure, and the results reveal that tunneling effects become increasingly pronounced at low gate voltages in devices with thinner oxides and thicker semiconductor thickness. These findings underscore the relevance of incorporating quantum tunneling mechanisms in predictive modeling of advanced transistor architectures.



Fig: Schematic FinFET device herein analyzed with confinement and transport directions (011) and <011>, respectively, and all the constant and varying geometrical parameters. Although FinFET is a 3D structure, it can be studied in a 2D approach, considering high aspect ratio fins (H>>TSi). In this 2D system, x and z are the transport and confinement directions, respectively; whereas y corresponds to the infinite direction. The 1D Schrödinger equation is solved for each grid point in the transport direction, and BTE is solved by the MC method in the transport plane.

Aug 20, 2025

IEEE SSCS DL at NXP Semiconductors, Munich

at NXP Semiconductors, Munich
Alvin Loke 
"The Road to Gate-All-Around and Its Impact on Analog Design"

Date/Time: 
11 Sep 2025 04:00 PM CEST to 06:30 PM CEST
Location: 
Schatzbogen 7; Munich, Bayern, Germany 81829
Building: NXP Semiconductors Germany GmbH
Host:
Germany Section Chapter, SSC37
Co-sponsored by NXP Semiconductors
Contact:


Abstract: Despite the much debated end of Moore's Law, CMOS scaling still maintains economic relevance with 3nm finFET SoCs already in the marketplace for over a year and 2nm gate-all-around SoCs anticipated this year. Modest feature size reduction and design/technology innovations co-optimized for primarily logic scaling continue to offer compelling node-to-node power, performance, area, and cost benefits. In this tutorial, we will start with a walk through memory lane, recounting a brief history of transistor evolution to motivate the migration from the planar MOSFET to the fully depleted FinFET. We will summarize the key process technology elements that have enabled the finFET CMOS nodes, highlighting the resulting device technology characteristics and challenges. This will set the context for motivating the introduction of the gate-all-around transistor architecture, namely nanoribbons or nanosheets, and unveiling the magic of how these devices are fabricated. We will then shift to summarize the challenges that CMOS technology scaling has imposed on analog design. To address the growing effort required for analog/mixed-signal design closure, we will cover design strategies on how analog design has adapted and thrived throughout decades of increasingly unfriendly CMOS scaling, including the migration to heterogeneous integration as prophesied by Gordon Moore's seminal 1965 paper.

BiographyAlvin Loke is a Senior Principal Engineer at Intel, San Diego, working on analog design/technology co-optimization for Intel's Angstrom-era CMOS. He has previously worked on CMOS nodes spanning 250nm to 2nm at Agilent, AMD, Qualcomm, TSMC, and NXP. He received a B.A.Sc. in engineering physics from the University of British Columbia, and M.S. and Ph.D. in electrical engineering from Stanford. After several years in CMOS process integration, Alvin has since worked on analog/mixed-signal design focusing on a variety of wireline links, design/model/technology interface, and analog design methodologies. Alvin has been an active IEEE Solid-State Circuits Society (SSCS) volunteer since 2003, having served as Distinguished Lecturer, AdCom Member, CICC Committee Member, Webinar Chair, Denver and San Diego Chapter Chair, as well as JSSC, SSCL, and Solid-State Circuits Magazine Guest Editor. He currently serves as the VLSI Symposium Secretary, SSCS Global Chapters Chair, and again as Distinguished Lecturer. Alvin has authored over 70 publications including the CICC 2018 Best Paper and invited short courses at ISSCC, VLSI Symposium, CICC, and BCICTS. He holds 29 US patents and recently received the ISSCC 2024 Outstanding Forum Speaker Award.

Aug 19, 2025

[paper] An Open-Source AMS Circuit Optimization

Z. Li and A. Chan Carusone
An Open-Source AMS Circuit Optimization Framework Based on Reinforcement Learning
From Specifications to Layouts
in IEEE Access, vol. 12, pp. 150032-150045 (2024) 
DOI: 10.1109/ACCESS.2024.3478832

Abstract: This paper presents a fully open-sourced AMS integrated circuit optimization framework based on reinforcement learning (RL). Specifically, given a certain circuit topology and target specifications, this framework optimizes the circuit in both schematic and post-layout phases. We propose using the heterogeneous graph neural network as the function approximator for RL. Optimization results suggest that it can achieve higher reward values with fewer iterations than the homogeneous graph neural networks. We demonstrate the applications of transfer learning (TL) in optimizing circuits in a different technology node. Furthermore, we show that by transferring the knowledge of schematic-level optimization, the trained RL agent can optimize the post-layout performance more efficiently than optimizing post-layout performance from scratch. To showcase the workflow of our approach, we extended our prior work to optimize latched comparators in the SKY130 and GF180MCU processes. Simulation results demonstrate that our framework can satisfy various target specifications and generate LVS/DRC clean circuit layouts.


FIG: Proposed AMS IC optimizer overview. 
The picture is adapted from [Z. Li and A. C. Carusone; 2023]

Acknowledgment: The authors would like to thank Dr. Hossein Shakiba from Huawei Technologies
for his valuable discussions throughout this project.

[REF] Z. Li and A. C. Carusone, "Design and optimization of low-dropout voltage regulator using relational graph neural network and reinforcement learning in open-source SKY130 process," in Proc. IEEE/ACM Int. Conf. Comput. Aided Design (ICCAD), Oct. 2023, pp. 1–9.


Aug 15, 2025

[mos-ak] Join the ICMC 2026 Organizing Team

International Compact Modeling Conference (ICMC) 2025 was a great success - thank you to everyone who contributed!  We're excited to announce that preparations are already underway for the next edition, taking place July 30–31, 2026 in Long Beach, California.

We are currently seeking enthusiastic volunteers to join the ICMC2026 organizing committees. If you're interested in helping shape next year's event, please complete the survey linked below:
https://survey.zohopublic.com/zs/bQfsUq

Submission deadline: August 25, 2025

📩 For questions about available roles, feel free to contact:

Shahed Reza, ICMC2026 General Chair or

Gert-Jan Smit, ICMC2026 Technical Program Chair

We look forward to your participation!

Thank you,
Leigh Anne Clevenger , Si2, on behalf of the ICMC2026 Organizing Committee

Aug 11, 2025

[mos-ak] [Final Program] 9th Sino MOS-AK Workshop Shenzhen

Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
9th Sino MOS-AK Workshop Shenzhen
August 14-16, 2025

We are pleased to invite you to participate in the 9th Sino MOS-AK Workshop, a premier forum for researchers, engineers, and industry professionals engaged in the device simulations, compact modeling, Verilog-A standardization, and advanced circuit design. This year's workshop will be hosted at SUSTech in Shenzhen, offering a dynamic program that blends cutting-edge research with practical insights. 

Venue:
  • Southern University of Science and Technology (SUSTech), Shenzhen, China
We look forward to your participation in this vibrant exchange of ideas and innovations. For registration and inquiries, please contact: music@sustech.edu.cn

-- Min Zhang and W.Grabinski on the behalf of International MOS-AK TPC Committee

Enabling Compact Modeling R&D Exchange

WG11082025

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Aug 7, 2025

[book] Guide to Characteristics and Characterization of Semiconductor Surfaces





Guide to Characteristics and Characterization 
of Semiconductor Surfaces
By: Jerzy Ruzyllo (Penn State University, USA)
https://doi.org/10.1142/12792 | May 2025 | Pages: 220





This comprehensive compendium explores aspects of semiconductor surface characteristics and characterization from the perspective of applied semiconductor device research and process development, rather than an in-depth coverage of surface science related issues. It provides guidance to the features of semiconductor surfaces affecting performance of the practical semiconductor devices, as well as selection of methods used to characterize those features.

Based on the author's over thirty years of research and graduate advising in semiconductor surface processing and characterization, this unique reference text addresses the needs of graduate students, researchers and industry professionals who are familiar with semiconductor engineering and would like to learn about the practical aspects of semiconductor surface characteristics, processing techniques, and characterization methods used in device process development, process diagnostics and monitoring.
  • FRONT MATTER i–xv
  • Chapter 1: Surface as a Part of Semiconductor Device Material System 1–14
  • Chapter 2: Effect of Surface on Characteristics of Semiconductor Materials 15–36
  • Chapter 3: Interactions of Semiconductor Surfaces 37–56
  • Chapter 4: Characteristics of Semiconductor Surface Defining its Condition 57–68
  • Chapter 5: Surface Effects in Semiconductor Devices 69–79
  • Chapter 6: Surface Processing in Semiconductor Device Technology 81–117
  • Chapter 7: Semiconductor Surface Characterization Methods 119–152
  • Chapter 8: Characterization of Semiconductor Surfaces in Process Monitoring 153–176
  • BACK MATTER 177–201

Aug 6, 2025

[mos-ak] IEEE SSCS-EDS South Brazil Chapter DL - IHP OpenPDK Initiative – Technology · Devices · Applications

The IEEE SSCS-EDS South Brazil Chapter, chaired by Juan Pablo Martinez Brito, PhD, to host Wladek Grabinski, PhD, a global expert in SPICE modeling and open-source IC design, for a Distinguished Lecture:

IHP OpenPDK Initiative – Technology · Devices · Applications
Date: August 13th, 2025
Time: 14h00 (GMT-3, Brasília)
IEEE SSCS-EDS South Brazil Chapter YouTube Channel

Dr. Grabinski will explore the growing role of FOSS CAD/EDA tools and OpenPDKs in strengthening the semiconductor ecosystem and enabling accessible IC design worldwide.

Thanks to the support of Unisinos, Federal University of Rio Grande do Sul, and UNIPAMPA Universidade Federal do Pampa RS, and to all the volunteers and engineers helping grow our regional chapter. Also, thank you to the chapter Board: Sandro Binsfeld Ferreira, Tiago Oliveira Weber, and Paulo César C. de Aguirre, and Professors Gilson Wirth and Sergio Bampi for the advice.

Looking forward to engaging with students, researchers, and professionals from across Brazil and beyond.


Add_To_Calendar_icon Add Event to Calendar
South Brazil Section Jt. Chapter,SSC37/ED15

#OpenPDK #SPICE #CompactModeling #Semiconductors #IEEE #ICDesign #FOSS #AnalogDesign #PDK #CMOS #IHP #SkyWater #GF #EDA #SouthAmericaSemiconductors #MOSAK #EDS #SSCS #UFRGS #Unisinos #Unipampa

WG060825


Aug 1, 2025

Low Cost Open Source MPW Access with IHP 130nm BiCMOS OpenPDK

Low Cost Open Source MPW Access 
with IHP 130nm BiCMOS OpenPDK
Terms and conditions
The mentioned prices below refer to the open-source designs, where all the views are compatible with the open source EDA tools.

For customers who do not wish to disclose their IP, we offer participation in the OpenMPW program at a 20% discount off the regular price, as the wafers can be shared with other customers. The turn around processing time is approx. 6 months for SG13CMOS and 8 months for SG13G2. Our/IHP basic offer contains 20 bare die samples. It is also possible to rent the wafer for measurements. Packaging will be offered on request (additional fee can be applied). 

Request/reserve your MPW IC Chip area online

Date of the upcoming MPW tapeout:  Optional run in November 2025, SG13CMOS

Total amount used by all customers: tbd

Price per mm²:
SG13CMOS – the initial price is 1500 EUR/mm² and it will scale down to 1000 EUR/mm² 
if the total area requested by all customers will be higher than 150 mm²
SG13G2 – fully featured G2 with AL BEOL at approx. 2800 EUR/mm²

SG13G2 Technology overview:
  • High speed SiGe HBT's featuring transit frequency (fT) of 350 GHz
  • Low/High voltage CMOS devices
  • 78 standard cells, IO-cells, a few fixed size SRAM
  • Regular ESD diodes, NMOS clamps
  • S-varicap
  • Schottky diodes
  • Polysilicon resistors, tap devices
  • MIM capacitor
  • 7 layer aluminium BEOL with 2 thick 3um top metal layers
  • [NB] SG13CMOS does not provide HBT's
IHP-Open-PDK Overview
  • Symbols for Xschem/Qucs-S
  • Ngspice models
  • Xyce models
  • Klayout support for layout, PyCells, DRC and LVS
  • Magic basic support (more to be finished until the end of the year)
  • OpenROAD-flow-script support
  • OpenEMS EM solver support
  • Measurements RAW data in MDM format

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