[mos-ak] [2nd Announcement and Call for Papers] 10th International MOS-AK Workshop in the Silicon Valley

10th International MOS-AK Workshop

(co-located with the CMC Meeting and IEDM Conference)

http://www.mos-ak.org/silicon_valley_2017/

Silicon Valley, December 6, 2017

2nd Announcement and Call for Papers 

Together with local organization teams Cadence Design Systems and Keysight Technologies as well as International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and all the Extended MOS-AK TPC Committee, we have pleasure to invite to the MOS-AK Compact Modeling Workshop which will be organized for consecutive 10th time in the timeframe of coming IEDM and CMC Meetings.

Planned,10th MOS-AK workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates: 

• Call for Papers - Sept. 2017
  
• 2nd Announcement - Oct. 2017
  
• Final Workshop Program - Nov. 2017
• MOS-AK Workshop - Dec.6, 2017 

Venue: 

Cadence Design Systems 

2655 Seely Ave

San Jose, CA 95134

Building 5 (map)

Topics to be covered include the following among other related to the compact/SPICE modeling :

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, TFT, CMOS and SOI-based memory cells
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS devices and circuits
• Technology R&D, DFY, DFT and reliability/ageing IC Designs
• Foundry/Fabless Interface Strategies

Prospective authors should submit abstract online

(any related inquiries can be sent to papers@mos-ak.org)

Online Workshop Registration

(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:

Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

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[paper] Review of physics-based compact models for emerging nonvolatile memories

Nuo Xu¹, Pai-Yu Chen², Jing Wang¹, Woosung Choi¹, Keun-Ho Lee³, Eun Seung Jung³, Shimeng Yu²

Review of physics-based compact models for emerging nonvolatile memories

¹Device Lab, Samsung Semiconductor Inc., San Jose, CA 95134, USA

²School of ECEE, Arizona State University, Tempe, AZ 85281, USA

³Semiconductor R&D Center, Samsung Electronics, Hwasung-si, Gyeonggi-do, Korea

Journal of Computational Electronics, 2017, pp. 1-13

https://doi.org/10.1007/s10825-017-1098-0

Abstract: A generic compact modeling methodology for emerging nonvolatile memories is proposed by coupling comprehensive physical equations from multiple domains (e.g., electrical, thermal, magnetic, phase transitions). This concept has been applied to three most promising emerging memory candidates: PCM, STT-MRAM, and RRAM to study their device physics as well as to evaluate their circuit-level performance. The models’ good predictability to experiments and their effectiveness in large-scale circuit simulation suggest their unique role in emerging memory research and development [read more...]

https://doi.org/10.1007/s10825-017-1098-0

SSCS Members Who Are 2017 IEEE Fellows

SSCS members who are IEEE Fellows pose with SSCS President, Jan Van der Spiegel and IEEE President, Karen Bartelson at ISSCC 2017. From left to right- Jan Van der Spiegel, Zhihua Wang, Andrei Vladimirescu, Carlo Samori, Borivoje Nikolic, Junichi Nakamura, Deog-kyoon Jeong, Hideto Hidaka, Payam Heydari, Edoardo Charbon, and Karen Bartleson 

How to pick a #winning #IoT #business #model https://t.co/YjMfxPAEZB https://t.co/SDOt080Ka6

How to pick a #winning #IoT #business #model https://t.co/YjMfxPAEZB http://pic.twitter.com/SDOt080Ka6

— Wladek Grabinski (@wladek60) October 30, 2017

from Twitter https://twitter.com/wladek60

October 30, 2017 at 03:39PM
via IFTTT

FOSDEM 2018 CAD and Open Hardware Devroom Call for Participation

(Also visible at https://www.ohwr.org/projects/ohr-meta/wiki/FOSDEM2018)

This is the call for participation in the FOSDEM 2018 devroom on Computer Aided Design (CAD) tools and Open Hardware, to be held on Saturday 3 February 2018 in Brussels, Belgium. We are looking for contributions under the form of talks and tutorials covering the following main topics:

• Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
• Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce,GHDL, Icarus and Verilator)
• Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen) and HDL synthesis tools (e.g. Yosys)
• Field solvers such as openEMS
• Mechanical 2D and 3D CAD tools such as LibreCAD, FreeCAD, OpenSCAD andSolveSpace
• Open Hardware projects such as the Teres laptop and the lowRISC SoC
• Inter-project opportunities for collaboration

We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS CAD and Open Hardware developments, share knowledge and identify opportunities to collaborate on development tasks. This devroom is an evolution of the EDA devroom we organised in 2015, 2016 and 2017.

The submission process: Please submit your proposals at

https://penta.fosdem.org/submission/FOSDEM18 before 1 December 2017.

If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one. Please provide a bit of information about yourself under Person -> Description -> Abstract. When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "CAD and Open Hardware Devroom" in the track drop-down menu. Otherwise your proposal might go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Bear in mind that a lot of the value in these meetings comes from the discussions, so please be reasonable regarding the duration of the talk.

Important dates

• 1 December 2017: deadline for submission of proposals
• 8 December 2017: announcement of final schedule
• 3 February 2018: devroom day

Recordings: The FOSDEM organisers hope to be able to live-stream and record all the talks. The recordings will be published under the same licence as all FOSDEM content (CC-BY). Only presentations will be recorded, not informal discussions and whatever happens during the lunch break. By agreeing to present at FOSDEM, you automatically give permission to be recorded. The organisers will agree to make exceptions but only for exceptional and well-reasoned cases.

Mailing list: Feel free to subscribe to the mailing list of the CAD and Open Hardware devroom to submit ideas, ask questions and generally discuss about the event:

https://lists.fosdem.org/listinfo/open-hardware-devroom

Spread the word!