[paper] Harmonic Distortion of GaN HEMT Varactors

Loukas Chevas 1,  Matthias Bucher 1,  Nikolaos Makris 1,2, Ioannis Spiridon Fosteris 1,  Nikolaos Fasarakis 1,  Antonios Stavrinidis 2,1, Maria Kayambaki 2,  Athanasios Kostopoulos 2 

and George Konstantinidis 2

Methodology for Harmonic Distortion Characterization and Modelling of GaN HEMT Varactors

Instruments 2026, 10(3), 37; 

DOI: 10.3390/instruments10030037

1 School of Electrical and Computer Engineering, Technical University of Crete, 73500 Chania, Greece
2 Institute of Electronic Structure and Laser, Foundation for Research and Technology-Hellas, 70013 Heraklion, Greece

Abstract: The bias-dependent capacitance of varactors can introduce harmonic distortion into the circuits where they are utilized. A gate capacitance model valid through inversion–depletion has been presented for GaN HEMT varactors in the drive for their utilization in monolithic GaN ASICs. This work focuses on the circuit and the methodology employed to accurately measure on wafer the harmonic distortion caused by one such device. The circuit is presented and its design considerations and operation trade-offs are discussed, followed by a presentation of the measurements resulting from its use. Second- and third-order harmonic distortion is recorded and presented, with Verilog-A model simulations used to fit the measured data. The model consists of a charge-based expression of the HEMT varactor capacitance, with a minimal number of parameters. The good fit of the model is demonstrated, proving both the suitability of the circuit used for the measurements and the validity of the capacitance model for real-world applications.  

Fig: Measurement setup schematic for the harmonic distortion characterization of HEMT varactors and V(f) characterization of the HEMT varactor. Inset is the parallel impedance combination measured by the LCR meter. (a) Cgc(Vg) for fixed frequencies. (b) Cgc(f) for fixed Vg levels. (c) Rp(Vg) for fixed frequencies. (d) Rp(f) for fixed Vg levels.

Aknowlegements: This research was partially funded by the European Union under the project AGAMI_EURIGAMI (ID:101102983).

Data Availability Statement: The measurement data generated and analyzed during the present study are available from the corresponding author upon reasonable request.

[mos-ak] [Final Program] 23rd MOS-AK/ESSERC Workshop in Palma de Mallorca (SP) Sept. 7, 2026

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

MOS-AK FOSS OpenPDK Workshop
ESSERC, Palma de Mallorca, Sept. 7 2026

The 23rd MOS‑AK/ESSERC Compact Modeling Workshop in Palma de Mallorca brings together the international community advancing SPICE/Verilog‑A modeling, OpenPDKs, and open‑source IC design flows. Since 2002 ESSEDRC/ESSCIRC in Porto, MOS‑AK has been the leading forum connecting technology developers, circuit designers, and FOSS CAD/EDA contributors, supporting knowledge exchange and strengthening the open semiconductor ecosystem. This year’s program showcases cutting‑edge developments: GaN MOS‑HEMT compact models for emerging OpenPDKs, AI/ML‑driven modeling workflows replacing manual tuning, cryogenic FD‑SOI model libraries, fully open‑source RFIC design case studies using IIC‑OSIC‑TOOLS, reliability insights for advanced CMOS and RF technologies, and a new OpenPDK MOSFET matching matrix IC enabling fast mismatch characterization. The workshop organizers are inviting engineers, researchers, and students who want a clear, practical view of modern device models and open simulation frameworks. It directly supports global OpenPDK adoption and aligns with European ODE4EC‑AMS activities, promoting accessible, reproducible, and future‑ready IC design methodologies. The MOS-AK workshop program is available online as well as with the direct link:

<https://www.mos-ak.org/palma_2026/>

Venue: ESSERC, Palma de Mallorca (SP)
Online Registration is OPEN (Early: until FRIDAY July 17, 2026)

MOS-AK ESSERC W7 Workshop Agenda

9:30 - 11:00	W7 Workshop Opening
T_1	ODE4EC-AMS OpenPDK: the Status and Roadmap Wladek Grabinski IHP OpenPDK (D)
T_2	Advanced in Verilog-A Model Standardization Arpad Buermen Uni. Ljubljana (SL)
T_3	Compact Modeling of GaN MOS-HEMTs for Open PDKs Ashkhen Yesayan EPFL (CH)
T_4	From Manual Tuning to Agentic AI: Transforming Device Modeling with AI/ML Roberto Tinti Keysight (US)
11:00 - 11:30	Coffee Break
T_5	Development of Cryogenic Model Libraries for FD-SOI Transistors Phanish Chava AdMOS (D)
T_6	Open-Source RFIC Design: Case Studies Using IIC-OSIC-TOOLS Georg Zachl JKU Linz (A)
T_7	Reliability topics for the miniaturization and qualification in OpenSilicon perspective Fernando Guarin IEEE EDS D1 (US)
T_8	OpenPDK MOSFET Matching Matrix IC Juan Brito CEITEC (BR)
13:00-14:00	End of the W7 Workshop and Lunch Break

W.Grabinski for Extended MOS-AK Committee

WG060726

[mos-ak] [C4P] Submissions Now Open for IEDM 2026

Submit a Paper Meeting Info Contact Us Submissions Now Open Deadline: July 16, 2026 The IEEE International Electron Devices Meeting Committee is seeking paper submissions for the 2026 IEDM Conference, themed “Devices at the Hearth of the Intelligence Revolution” We invite contributions from various areas of expertise (view all suggested topics).  Format: Papers must be submitted electronically in a PDF format, compatible with IEEE Xplore Guidelines: Before preparing your paper, please review the paper preparation and submission guidelines on our website where you’ll find a paper template, sample paper and additional preparation details. Presentation: Accepted papers MUST be presented in person at the conference AND authors must submit a pre-recording of their presentation for OnDemand registrants. Call for Papers Info Student Papers We highly encourage student submissions. Papers presented by students based on their own work are eligible for the Best Student Paper Award. To be considered, the paper must be identified as a student paper during submission. The award will be judged on the paper's quality and its presentation, which must be delivered by the student. The winner of the award will be announced and honored at IEDM 2027. MEETING HIGHLIGHTS IEDM is the world’s preeminent forum for reporting technological breakthroughs in semiconductor and electronic device technology, design, manufacturing, physics, and modeling. The conference will feature: Three plenary presentations  Special focus sessions  Evening panel discussions  Tutorial sessions Short Courses  Mark your calendar for December 12-16, 2026, and join us in San Francisco, CA. Attendee:  For more information IEDM Online Email: info@ieee-iedm.org Social Networks (Info/Follow) IEDM | Canfield Event Management, LLC | +1 972 521-9902 | ieee-iedm@cemllc.com

IEDM | 445 Hoes Lane | Piscataway, NJ 08854 US

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[paper] SPICE-Q Quantum Chip Production

Ling Qiao Cai1,2, Bin Yang1,2, Fumin Luo1,2, Chang Liu1,2, WeiGui Guo1,2, GuoRong Zhang1,2, XueFei Liu1,2, Qinglang Guo1,2 and Bin Wu

SPICE-Q and Large-Scale Quantum Chip Production

[quant-ph] 16 Jun 2026 

arXiv:2606.17907v1  

1.) Yangtze Delta Industrial Innovation Center of Quantum Science and Technology, Suzhou, (CN)
2.) China Academy of Electronics and Information Technology, No. 11 Shuangyuan Road, Shijingshan District, Beijing, (CN)

Abstract: The historical analogy with SPICE is based on foundational reports, numerical methods, and experience from integrated circuit design. The requirements for quantum computing and scaling refer to established work in the field. The background on superconducting qubits, transmons, circuit quantum electrodynamics, microwave networks, material loss, and three‑dimensional interconnects draw from widely recognized literature. The background on parameter extraction, simulation frameworks, and manufacturability is informed by recent research and practical developments.

Table of Contents (Top‑Level Sections)

1. Abstract ... p. 4
2. The Emergence of SPICE and Large‑Scale Classical Circuits
   and Its Implications for Quantum Chips ... p. 5
3. SPICE‑Q Model Composition ... p. 24
4. SPICE‑Q Device‑Level Models ... p. 40
5. Standardized Manufacturing System ... p. 53
6. Integrating SPICE‑Q with Process Models ... p. 66
7. Design‑Technology Co‑Optimization (DTCO) ... p. 71
8. Large‑Scale Production Examples and Design Scenarios ... p. 75
9. Engineering Transition and Large‑Scale Quantum Chips ... p. 80
10. Summary ... p. 84
11. Acknowledgment ... p. 87
12. Reference ... p. 87
13. Appendix A ... p. 90

Acknowledgment The authors thank Jun Ye for helpful assistance. The authors also acknowledge the use

of AI tools for translation assistance and auxiliary text generation.

[paper] 130-nm CMOS tunnel p-bit cell

Ju-Young Yoon, Nuno Caçoilo, Advait Madhavan, Jabez J. McClelland, Shun Kanai, Hideo Ohno, Shunsuke Fukami, and William A. Borders, 

"130-nm CMOS-integrated superparamagnetic tunnel junction-based p-bit," 

in IEEE Electron Device Letters, 

DOI: 10.1109/LED.2026.3696800

Abstract: Probabilistic computers offer promising solutions for computationally hard problems in domains such as combinatorial optimization and machine learning. A key building block in these systems is the probabilistic bit (p-bit), which relies on superparamagnetic tunnel junctions (sMTJs) as its source of randomness. A challenging threshold to cross for scaling sMTJ-based p-bit systems is integration of sMTJs with CMOS technology. In this work, we present experimental results of a p-bit unit cell using sMTJs integrated with 130 nm CMOS technology and demonstrate that the sMTJ’s resistance fluctuations can generate a corresponding fluctuating digital output voltage which is tunable via the input voltage. These findings establish the feasibility of CMOS-compatible, sMTJ-based probabilistic circuits and mark a key step toward scalable hardware for real-world probabilistic computing applications. 

FIG: (a) Circuit diagram of the spintronic p-bit; b) Schematic cross-sectional structure of the spintronic p-bit. Transistors and lower interconnect layers were fabricated at SkyWater, followed by fabrication of the spintronic devices at Uni. Tohoku. (c,d) Cross-sectional and plan-view electron microscope images of the spintronic device designed to exhibit stochastic fluctuations.

Acknowledgements: This work was made possible by the NIST-led Nanotechnology Xccelerator program that distributes open-source circuit designs for integration of novel technologies on CMOS.