[paper] Nanowire Biosensor Analytical Model

Ashkhen Yesayan, Aleksandr Grabski, Farzan Jazaeri, Jean-Michel Sallese

Design-Oriented Analytical Model for Nanowire Biosensors Including Dynamic Aspects

IEEE TED (2025) DOI 10.1109/TED.2025.3526113

Abstract: Nanowire Field Effect Transistor (NWFET) biosensors are known to be highly sensitivity devices that can detect extremely low concentrations of biomolecules. In this paper, we present an analytical model alongside with numerical simulations to calculate the sensitivity of NWFET biosensors. The model accounts for biosensing dynamics as well as diffusion of ions in the solution and across the functionalized layer. The signal-to-noise ratio is also estimated, which gives a lower limit in terms of sensitivity. The model is physics based and is validated against a commercial multiphysics simulations and experimental data. It predicts the bio-sensitivity down to femtomolar concentration of biomolecules without any fitting parameter.

FIG: Schematic structure of device (a), the charge distribution in theoretical model (b) 

and Si NWFET sensitivity simulated with presented model (c)

Acknowledgement: This work was supported by the Science Committee of RA, in the frames of the research project No:21T-2B321.

SwissChips: foster the Swiss semiconductor ecosystem

SwissChips is an inital three-year transitional measure jointly led by the Swiss Center for Electronics and Microtechnology (CSEM), EPFL and ETH, aimed to maintain and secure a strong position of Swiss researchers and research infrastructure in the strategically important areas of semiconductor technologies, microelectronics, and more specifically cutting-edge integrated circuit (IC) design within the European landscape [read more...]

[paper] Spatz: open-source RISC-V compact VPU

Matteo Perotti, Samuel Riedel, Matheus Cavalcante and Luca Benini^1,2

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency

arXiv:2309.10137v2 [cs.AR] 9 Jan 2025

1 IIS, ETH Zurich (CH)
2 DEI, Uni. Bologna (IT)

Abstract: The ever-increasing computational and storage requirements of modern applications and the slowdown of technology scaling pose major challenges to designing and implementing efficient computer architectures. To mitigate the bottlenecks of typical processor-based architectures on both the instruction and data sides of the memory, we present Spatz, a compact 64-bit floating-point-capable vector processor based on RISC-V’s Vector Extension Zve64d. Using Spatz as the main Processing Element (PE), we design an open-source dual-core vector processor architecture based on a modular and scalable cluster sharing a Scratchpad Memory (SCM). Unlike typical vector processors, whose Vector Register Files (VRFs) are hundreds of KiB large, we prove that Spatz can achieve peak energy efficiency with a latch-based VRF of only 2 KiB. An implementation of the Spatz-based cluster in GlobalFoundries’ 12LPP process with eight double-precision Floating Point Units (FPUs) achieves an FPU utilization just 3.4% lower than the ideal upper bound on a double-precision, floating-point matrix multiplication. The cluster reaches 7.7 FMA/cycle, corresponding to 15.7 GFLOPSDP and 95.7 GFLOPSDP/W at 1 GHz and nominal operating conditions (TT, 0.80 V, 25 °C), with more than 55% of the power spent on the FPUs. Furthermore, the optimally-balanced Spatz-based cluster reaches a 95.0% FPU utilization (7.6 FMA/cycle), 15.2 GFLOPSDP, and 99.3 GFLOPSDP/W (61% of the power spent in the FPU) on a 2D workload with a 7 × 7 kernel, resulting in an outstanding area/energy efficiency of 171 GFLOPSDP/W/mm2. At equi-area, the computing cluster built upon compact vector processors reaches a 30% higher energy efficiency than a cluster with the same FPU count built upon scalar cores specialized for streambased floating-point computation.

Fig: Placed-and-routed Spatz-based shared-L1 cluster, implemented as a 737 μm × 1003 μm block. The cluster’s main blocks are highlighted: namely the Snitch cores, VRFs, IPUs, FPUs, L1 SPM, and I$.

Acknowledgment: This work was supported in part through the TRISTAN (#101095947) and the ISOLDE (#101112274) projects, both funded through the Chips Joint Undertaking (CHIPS JU) of the European Union’s Horizon Europe’s research and innovation programme and its members.

[book] From Code to Chip

Jakob Ratschenberger and Harald Pretl

From Code to Chip:

Open-Source Automated Analog Layout Design

pp: XV, 120 Publisher: Springer Cham (10 January 2025)

eBook ISBN 978-3-031-68562-0

This book shows how the layout of an analog circuit can be automatically generated in a fully open-source way. Based on an exemplary design flow, it introduces and explains the necessary steps for transforming a SPICE netlist into a layout, which can be inspected by the open-source layout editor Magic VLSI. This is done by using the industry’s first open-source process design kit SKY130. Furthermore, the implementation of the design flow in the programming language Python is available as open-source on GitHub. 

Authors' Affiliations

Johannes Kepler University, Linz, Austria

Table of contents (8 chapters)

• Front Matter pp. i-xv
• Download chapter PDF 
• Introduction pp. 1-4
• Theoretical Basics pp. 5-13
• Circuit Capturing pp. 15-36
• PDK—Design Rule Capturing pp. 37-41
• Placement pp. 43-55
• Routing pp. 57-71
• Experimental Results pp. 73-99
• Outlook pp. 101-103
• Back Matter pp. 105-120

 

[paper] Compact Model of Linear Passive IPD

Zhang, Zijian

Compact Model of Linear Passive Integrated Photonics Device

for Photon Design Automation

arXiv preprint: 2501.06774 (2025)

1 University of Electronic Science and Technology of China, Chengdu, 611731, China

Abstract: As integrated photonic systems grow in scale and complexity, Photonic Design Automation (PDA) tools and Process Design Kits (PDKs) have become increasingly important for layout and simulation. However, fixed PDKs often fail to meet the rising demand for customization, compelling designers to spend significant time on geometry optimization using FDTD, EME, and BPM simulations. To address this challenge, we propose a data-driven Eigenmode Propagation Method (DEPM) based on the unitary evolution of optical waveguides, along with a compact model derived from intrinsic waveguide Hamiltonians. The relevant parameters are extracted via complex coupled-mode theory. Once constructed, the compact model enables millisecond-scale simulations that achieve accuracy on par with 3D-FDTD, within the model’s valid scope. Moreover, this method can swiftly evaluate the effects of manufacturing variations on device and system performance, including both random phase errors and polarization-sensitive components. The data-driven EPM thus provides an efficient and flexible solution for future photonic design automation, promising further advancements in integrated photonic technologies.

Fig: Photon design automation workflow based on compact model

of linear passive optical waveguide

Supplementary information:

The time evaluations were conducted on a system equipped with an Intel i9-10850K processor, 64 GB DDR4 memory, and NVIDIA Quadro RTX 5000 professional graphics processor.