[paper] Scalable Open-Source Multi-Project SoC Architecture

Uriel Jaramillo-Toral, Susana Ortega-Cisneros, Héctor Emmanuel Muñoz-Zapata, 

Iraam Antonio López-Salas 

Silicluster v2: A Scalable Open-Source Multi-Project SoC Architecture 

in Sky130 CMOS Enabling High-Density Modular Integration

in IEEE Access, vol. 14, pp. 82876-82889, 2026

doi: 10.1109/ACCESS.2026.3698053. 

* CINVESTAV, Guadalajara, Jalisco, Mexico

* Tecnológico Nacional de México, ITA, Aguascalientes, Mexico

Abstract: The increasing availability of open-source electronic design automation (EDA) tools and publicly accessible process design kits (PDKs) has expanded access to integrated circuit (IC) development; however, scalable system-level integration frameworks capable of supporting heterogeneous digital, analog, and mixed-signal systems remain limited. This paper presents Silicluster Version 2 (Silicluster v2), a hierarchical and scalable multi-project system-on-chip (SoC) architecture implemented in 130 nm complementary metal-oxide-semiconductor (CMOS) technology using a fully open-source register-transfer-level (RTL) to Graphic Data System II (GDSII) layout design flow. The proposed architecture enables the structured integration of up to 256 independent digital, analog, and mixed-signal modules within a single chip while preserving modular isolation, reusability, and routing efficiency. In contrast to its previous digital-focused implementation, Silicluster v2 incorporates infrastructure supporting transistor-level analog layout, parasitic-aware mixed-domain co-simulation using Simulation Program with Integrated Circuit Emphasis (SPICE), and integration of synthesized standard-cell netlists alongside custom transistor-level blocks. A hierarchical multiplexed interconnection scheme and centralized clock-distribution strategy mitigate fanout, congestion, and timing-closure challenges inherent to high-density modular integration. The complete system is validated through design rule checking (DRC), layout-versus-schematic (LVS) verification, parasitic extraction, and static timing analysis (STA) at 10 MHz, targeting 1.8 V digital operation and 3.3 V analog operation. The results demonstrate the feasibility of constructing complex heterogeneous integrated circuits using exclusively open-source methodologies, establishing Silicluster v2 as a validated reference architecture for collaborative silicon integration and scalable multi-project chip development.

Fig: Graphical representation of the Silicluster v2 integration process within Caravel. The original user area is replaced by the Silicluster v2 wrapper, enabling high-density modular integration and resulting in a complete MPW-ready SoC while preserving the RISC-V subsystem and padframe infrastructure.

Acknowledgment: The authors gratefully recognize ChipFoundry for enabling the fabrication of Silicluster v2 through the MPW Program. Their support made the physical realization of the proposed architecture possible. They also acknowledge Toyohashi University of Technology (TUT) for its early-stage mentorship in analog design methodologies and the Centro de Investigación y de Estudios Avanzados del IPN, Unidad Guadalajara (CINVESTAV), for providing the academic environment and institutional framework that supported the development of this project.

[paper] Spatz: open-source RISC-V compact VPU

Matteo Perotti, Samuel Riedel, Matheus Cavalcante and Luca Benini^1,2

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency

arXiv:2309.10137v2 [cs.AR] 9 Jan 2025

1 IIS, ETH Zurich (CH)
2 DEI, Uni. Bologna (IT)

Abstract: The ever-increasing computational and storage requirements of modern applications and the slowdown of technology scaling pose major challenges to designing and implementing efficient computer architectures. To mitigate the bottlenecks of typical processor-based architectures on both the instruction and data sides of the memory, we present Spatz, a compact 64-bit floating-point-capable vector processor based on RISC-V’s Vector Extension Zve64d. Using Spatz as the main Processing Element (PE), we design an open-source dual-core vector processor architecture based on a modular and scalable cluster sharing a Scratchpad Memory (SCM). Unlike typical vector processors, whose Vector Register Files (VRFs) are hundreds of KiB large, we prove that Spatz can achieve peak energy efficiency with a latch-based VRF of only 2 KiB. An implementation of the Spatz-based cluster in GlobalFoundries’ 12LPP process with eight double-precision Floating Point Units (FPUs) achieves an FPU utilization just 3.4% lower than the ideal upper bound on a double-precision, floating-point matrix multiplication. The cluster reaches 7.7 FMA/cycle, corresponding to 15.7 GFLOPSDP and 95.7 GFLOPSDP/W at 1 GHz and nominal operating conditions (TT, 0.80 V, 25 °C), with more than 55% of the power spent on the FPUs. Furthermore, the optimally-balanced Spatz-based cluster reaches a 95.0% FPU utilization (7.6 FMA/cycle), 15.2 GFLOPSDP, and 99.3 GFLOPSDP/W (61% of the power spent in the FPU) on a 2D workload with a 7 × 7 kernel, resulting in an outstanding area/energy efficiency of 171 GFLOPSDP/W/mm2. At equi-area, the computing cluster built upon compact vector processors reaches a 30% higher energy efficiency than a cluster with the same FPU count built upon scalar cores specialized for streambased floating-point computation.

Fig: Placed-and-routed Spatz-based shared-L1 cluster, implemented as a 737 μm × 1003 μm block. The cluster’s main blocks are highlighted: namely the Snitch cores, VRFs, IPUs, FPUs, L1 SPM, and I$.

Acknowledgment: This work was supported in part through the TRISTAN (#101095947) and the ISOLDE (#101112274) projects, both funded through the Chips Joint Undertaking (CHIPS JU) of the European Union’s Horizon Europe’s research and innovation programme and its members.