[book] Tunneling Field Effect Transistors

Tunneling Field Effect Transistors
Design, Modeling and Applications

Edited By T. S. Arun Samuel, Young Suh Song, Shubham Tayal, P. Vimala, Shiromani Balmukund Rahi

ISBN 9781032348766
1st Edition; 316 Pages; 15 Color & 232 B/W Illustrations
June 8, 2023 by CRC Press

Description: This book will give insight into emerging semiconductor devices from their applications in electronic circuits, which form the backbone of electronic equipment. It provides desired exposure to the ever-growing field of low-power electronic devices and their applications in nanoscale devices, memory design, and biosensing applications.

Tunneling Field Effect Transistors: Design, Modeling and Applications brings researchers and engineers from various disciplines of the VLSI domain to together tackle the emerging challenges in the field of nanoelectronics and applications of advanced low-power devices. The book begins by discussing the challenges of conventional CMOS technology from the perspective of low-power applications, and it also reviews the basic science and developments of subthreshold swing technology and recent advancements in the field. The authors discuss the impact of semiconductor materials and architecture designs on TFET devices and the performance and usage of FET devices in various domains such as nanoelectronics, Memory Devices, and biosensing applications. They also cover a variety of FET devices, such as MOSFETs and TFETs, with various structures based on the tunneling transport phenomenon.

The contents of the book have been designed and arranged in such a way that Electrical Engineering students, researchers in the field of nanodevices and device-circuit codesign, as well as industry professionals working in the domain of semiconductor devices, will find the material useful and easy to follow.

Table of Contents:

Chapter 1. Challenges of Conventional Cmos Technology in Perspective of Low Power Applications

Chapter 2. Basic Science and Development of Subthreshold Swing Technology

Chapter 3. Historical Development of MOS technology to Tunnel FETs

Chapter 4. Modeling of Gate Engineered TFETs: Challenges and Opportunities

Chapter 5. Modeling of Gate Engineered TFET: challenges and Opportunities.

Chapter 6. Evolution of Heterojunction Tunnel Field Effect Transistor and its Advantages

Chapter 7. Analog / RF performance analysis of TFET device

Chapter 8. DC Analysis and Analog/HF Performances of GAA-TFET with Dielectric Pocket

Chapter 9. Investigation on Ambipolar Current Suppression in Tunnel FETs

Chapter 10. Analysis of Channel Doping Variation on Transfer Characteristics to High Frequency performance of F-TFET

Chapter 11. Design of Nanotube TFET Biosensor

Chapter 12. TFET-based Memory Cell Design with Top-down Approach

Chapter 13. Designing of nonvolatile memories utilizing Tunnel Field Effect Transistor

Chapter 14. TFET-based Universal

Chapter 15. TFET-based Level Shifter Circuits for Low Power Applications

[Commemorative] History of Junction Technologies

Hiroshi Iwai

History of Junction Technologies

Commemorative talk for the 75th anniversary of the transistor

IWJT 2023; T-Cosponsored by IEEE EDS; 

Kyoto (J) June 8-9, 2023

1 International College of Semiconductor Technology, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
2 Tokyo Institute of Technology, Japan

Abstract: In this paper, I describe the history of junction technologies for ICT (Information and Communication Technology) devices. Junctions serve as functional interfaces between materials in these devices. Over the past 200 years, since the inception of electrical engineering, a wide range of junction technologies have been developed as key components for device operation, playing a significant role in advancing intelligence in human society.

FIG: The first idea of FET (MISFET) by J. Lilienfeld "Method and apparatus for controlling electric current", Canadian Patent CA272437TA, filed October 22, 1925

Acknowledgements: I [author: Hiroshi Iwai] would like to express my sincere appreciation to the Tokyo Institute of Technology Library for granting me access to historically significant documents. The information available on the Computer History Museum (CHM) website was instrumental in understanding the timeline of device development. I am deeply grateful to Prof. Kazuo Tsutsui of Tokyo Institute of Technology for providing me with a conducive environment to concentrate on writing this manuscript. I would also like to extend my gratitude to the IWJT committee members for granting me the valuable opportunity to document the history of junction technologies, logic and memory device technologies, as well as reviewing the lengthy manuscript. In particular, I am grateful to Dr. Michael Current for his meticulous review of the manuscript. Finally, I would like to thank my colleagues in both industry and academia who have dedicated their time and expertise to the advancement of integrated circuit technology over the years.

[paper] Perovskite Photodiodes

Dong Li and Anlian Pan

Perovskite sensitized 2D photodiodes

Light Sci Appl 12, 139 (2023)

DOI: 10.1038/s41377-023-01187-2

Key Laboratory for Micro-Nano Physics and Technology of Hunan Province, State Key Laboratory of Chemo/Biosensing and Chemometrics, Hunan Institute of Optoelectronic Integration, College of Materials Science and Engineering, Hunan University, Changsha, China

Abstract: A new type of perovskite sensitized programmable WSe2 photodiode is constructed based on MAPbI3/WSe2 heterojunction, presenting flexible reconfigurable characteristics and prominent optoelectronic performances. The unique design of MAPbI3/WSe2 device provides a new idea to fabricate high-performance programmable photodiodes. In addition, the combination of atomic thin 2D materials and ionic solids enables effective coupling between electronic transport and ionic transport, which may open up a new pathway for unconventional computing, information storage systems, and programmable optoelectronic devices.

FIG: Schematic view of MAPbI3/WSe2 device structure and working mechanism 

of the programmable perovskite sensitized WSe2 photodiode

[paper] Teaching Traditional TCAD New Tricks

Sanghoon Myung¹, Wonik Jang¹, Seonghoon Jin²

Myung Choe¹, Changwook Jeong¹, and Dae Sin Kim¹

Restructuring TCAD System:

Teaching Traditional TCAD New Tricks

DOI: 10.1109/IEDM19574.2021.9720616

1Data and Information Technology Center, Samsung Electronics.
2Device Lab, Samsung Semiconductor Inc.

Abstract : Traditional TCAD simulation has succeeded in predicting and optimizing the device performance; however, it still faces a massive challenge - a high computational cost. There have been many attempts to replace TCAD with deep learning, but it has not yet been completely replaced. This paper presents a novel algorithm restructuring the traditional TCAD system. The proposed algorithm predicts three-dimensional (3D) TCAD simulation in real-time while capturing a variance, enables deep learning and TCAD to complement each other, and fully resolves convergence errors.

Fig: (a) A TCAD process simulation result. (b) A prediction result of RTT process model.

(c) 1D doping concentration plot in the horizontal direction below the gate.

(d) 1D doping concentration plot in the vertical direction at the center of drain.

[PhD Thesis] Digital-based analog processing in nanoscale CMOS ICs for IoT applications

Digital-based analog processing in nanoscale CMOS ICs for IoT applications

http://hdl.handle.net/10183/249786

PhD Cadndiate: Pedro Filipe Leite Correia De Toledo

Universidade Federal do Rio Grande do Sul. Instituto de Informática

Programa de Pós-Graduação em Microeletrônica.

Advisor: Klimach, Hamilton Duarte

Co-advisor: Crovetti, Paolo Stefano

Abstract: The Internet-of-Things (IoT) concept has been opening up a variety of applications, such as urban and environmental monitoring, smart health, surveillance, and home automation. Most of these IoT applications require more and more power/area efficient Complemen ary Metal–Oxide–Semiconductor (CMOS) systems and faster prototypes (lower time-to market), demanding special modifications in the current IoT design system bottleneck: the analog/RF interfaces. Specially after the 2000s, it is evident that there have been significant improvements in CMOS digital circuits when compared to analog building blocks. Digital circuits have been taking advantage of CMOS technology scaling in terms of speed, power consumption, and cost, while the techniques running behind the analog signal processing are still lagging. To decrease this historical gap, there has been an increasing trend in finding alternative IC design strategies to implement typical analog functions exploiting Digital in-Concept Design Methodologies (DCDM). This idea of re-thinking analog functions in digital terms has shown that Analog ICs blocks can also avail of the feature-size shrinking and energy efficiency of new technologies. This thesis deals with the development of DCDM, demonstrating its compatibility for Ultra-Low-Voltage (ULV) and Power (ULP) IoT applications. This work proves this statement through the proposing of new digital-based analog blocks, such as an Operational Transconductance Amplifiers (OTAs) and an ac-coupled Bio-signal Amplifier (BioAmp). As an initial contribution, for the first time, a silicon demonstration of an embryonic Digital-Based OTA (DB-OTA) published in 2013 is exhibited. The fabricated DB-OTA test chip occupies a compact area of 1,426 µm2 , operating at supply voltages (VDD) down to 300 mV, consuming only 590 pW while driving a capacitive load of 80pF. With a Total Harmonic Distortion (THD) lower than 5% for a 100mV input signal swing, its measured small-signal figure of merit (FOMS) and large-signal figure of merit (FOML) are 2,101 V −1 and 1,070, respectively. To the best of this thesis author’s knowledge, this measured power is the lowest reported to date in OTA literature, and its figures of merit are the best in sub-500mV OTAs reported to date. As the second step, mainly due to the robustness limitation of previous DB-OTA, a novel calibration-free digital-based topology is proposed, named here as Digital OTA (DIG OTA). A 180-nm DIGOTA test chip is also developed exhibiting an area below the 1000 µm2 wall, 2.4nW power under 150pF load, and a minimum VDD of 0.25 V. The proposed DIGOTA is more digital-like compared with DB-OTA since no pseudo-resistor is needed. As the last contribution, the previously proposed DIGOTA is then used as a building block to demonstrate the operation principle of power-efficient ULV and ultra-low area (ULA) fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA) such as extreme low area Body Dust. Measured results in 180nm CMOS confirm that the proposed BioDIGOTA can work with a supply voltage down to 400 mV, consuming only 95 nW. The BioDIGOTA layout occupies only 0.022 mm2 of total silicon area, lowering the area by 3.22X times compared to the current state of the art while keeping reasonable system performance, such as 7.6 Noise Efficiency Factor (NEF) with 1.25 µVRMS input-referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of the common-mode rejection ratio (CMRR) and 55 dB of power supply rejection ratio (PSRR). After reviewing the current DCDM trend and all proposed silicon demonstrations, the thesis concludes that, despite the current analog design strategies involved during the analog block development

Fig: a) analog design octagon; b) gm/ID·fT versus the inversion coefficient IC, λc is the parameter corresponding to the fraction of the channel in which the carrier drift velocity reaches the saturated velocity over a portion of the channel geometrical length; c) Performance difference between analog and digital blocks over time; d) Area reduction over the years of the bitcell SRAM, OTA and bandgap reference