We Could Really Have a #Wireless #Power Grid That Runs on #5G https://t.co/13ndWwPnBK #semi pic.twitter.com/ouljqCRVB0
— Wladek Grabinski (@wladek60) May 5, 2021
from Twitter https://twitter.com/wladek60
May 05, 2021 at 09:07AM
via IFTTT
May 5, 2021
We Could Really Have a #Wireless #Power Grid That Runs on #5G
from Twitter https://twitter.com/wladek60
May 05, 2021 at 09:07AM
via IFTTT
May 4, 2021
[paper] Random Telegraph Noise in Metal‐Oxide Memristors
[paper] Li, X., Zanotti, T., Wang, T., Zhu, K., Puglisi, F. M., Lanza, M., Random Telegraph Noise in Metal‐Oxide Memristors for True Random Number Generators: A Materials Study. Adv. Funct. Mater. 2021, 2102172. https://t.co/VuSUNNZbm4 https://t.co/xxa3wRpRSp#semi pic.twitter.com/8CSdM5cmYk
— Wladek Grabinski (@wladek60) May 4, 2021
from Twitter https://twitter.com/wladek60
May 04, 2021 at 02:37PM
via IFTTT
[Si2 CMC] to Standardize SPICE Model for SiC MOSFET
May 03, 2021 // By Peter Clarke [eenewsanalog.com]
The Compact Model Coalition (CMC) working group of the Silicon Integration Initiative (SI2) has agreed to standardize a model for the behaviour of a silicon-carbide MOSFET.
The Compact Model Coalition (CMC) working group of the Silicon Integration Initiative (SI2) has agreed to standardize a model for the behaviour of a silicon-carbide MOSFET.
Silicon-carbide offers higher efficiency and faster operation than silicon and has been adopted for several power applications including photovoltaic inverters and converters, industrial motor drives, electric vehicle powertrain and EV charging, and power supply and distribution. A CMC working group will oversee the model development with Analog Devices, Cadence Design Systems, Infineon, Qualcomm, Siemens EDA, Silvaco and Synopsys set to participate.
"I'd encourage companies with a stake in silicon-carbide devices to join this effort and help guide selection of the model which best represents their intended use,"
advised Peter Lee, chair of the CMC.
Now in its 25th year, the Si2 Compact Model Coalition provides semiconductor manufacturers, designers, and simulation tool providers a means to pool resources to fund standardization and optimization of standard compact SPICE models and standard interfaces to promote simulation tool interoperability [Read more...]
May 3, 2021
[paper] FET Library for VLSI
Taehak Kim1, Jaehoon Jeong2, Seungmin Woo2, Jeonggyu Yang1, Hyunwoo Kim2 Ahyeon Nam2, Changdong Lee2, Jinmin Seo2, Minji Kim2, Siwon Ryu2, Yoonju Oh2, and Taigon Song1,2
NS3K : A 3nm Nanosheet FET Library for VLSI Prediction in Advanced Nodes
IEEE ISCAS, 2021, pp. 1-5, DOI 10.1109/ISCAS51556.2021.9401055.
1School of Electronics Engineering, Kyungpook National University (KNU), Daegu 41566, South Korea
2School of Electronic and Electrical Engineering, Kyungpook National University (KNU), Daegu 41566, South Korea
Abstract: Nanosheet FETs (NSFETs) are expected as future devices that replace FinFETs beyond the 5nm node. Despite the importance of the devices, few studies report the impact of NSFETs in the full-chip level. Therefore, this paper presents NS3K, the first 3nm NSFET library, and presents the results in a full-chip scale. Based on our results, 3nm NSFET reduces power by -27.4%, total wirelength by -25.8%, number of cells by -8.5%, and area by -47.6% over 5nm FinFET, respectively, due to better devices and interconnect scaling. However, careful device/layout designs followed by routing-resource considering standard cells are required to maximize the advantages of 3nm technology.
Fig: Projected 3nm NSFET library development flow. Upper side of each step shows the names of required tools. Each colored-boxes correspond to the steps required for specific tasks: The blue boxes - device development, the orange boxes - digital design, and the green boxes - back end design, respectively.
Acknowledgements: This research was supported by National R&D Program through the National Research Foundation of Korea (NRF) funded by Ministry of Science and ICT (2020M3H2A1078045). The EDA tool was supported by the IC Design Education Center(IDEC), Korea. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No.2019R1G1A109470212).
[paper] Compact modeling of lab-on-chip
Alexi Bonament, Morgan Madec and Christophe Lallement
Compact modeling of reaction-diffusion-advection mechanisms
for the virtual prototyping of lab-on-chip
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1-5,
doi: 10.1109/ISCAS51556.2021.9401396.
Abstract: The topic of this paper is the development of compact models reaction-advection-diffusion phenomenon compatible with a SPICE simulation environment. From a mathematical perspective, biological systems that involve such phenomena are described by partial differential equations, which are not naturally handeled by SPICE. Our approach consists of discretizing these equations according to the finite-difference method and converting the resulting set of ordinary differential equations into an assembly of elementary equivalent electronic circuits written in Verilog-A. The main interest of this approach is the capability of coupling such models with third-party SPICE models of electronic circuits, sensors and transducers as well as biochemical models that can also be written in SPICE. The tool is validated both on simple problems for which analytical solutions are known and by comparison with a finite element simulator of reference
Fig: Core modules of the designed tool. Labels indicate the programming language.
Acknowledgment: This research was supported by the European Regional Development Fund (ERDF) and the Interreg V Upper Rhine Offensive Sciences Program (Project 3.14 – Water Pollution Sensor).
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