May 5, 2014

IJNM Call for Papers

Advances in simulation-driven modeling and optimization of microwave/RF circuits
IJNM Call for Papers

Computer-aided modeling and design of microwave/radio frequency (RF) devices and circuits have undergone tremendous developments in the past decade. The complexity of today's devices and circuits renders electromagnetic (EM) simulation a sine qua non in the microwave design process. That said, EM-driven design poses significant challenges, mostly due to the high computational cost of accurate, high-fidelity simulation. The availability of massive computational resources does not always translate into design speedup because of the need to account for interactions between devices and their surroundings as well as multi-physics (e.g., EM-thermal) effects. Not surprisingly, traditional design optimization procedures that directly utilize EM-simulated responses typically fail or are impractical. As a consequence, there is growing interest in alternative optimization and modeling methodologies, especially ones that exploit computationally cheap surrogate models.
This Special Issue focuses on the current state of the art and future directions in microwave and RF design. Papers on software engineering and practical applications aspects are also encouraged. Suitable topics for this Special Issue therefore include but are not limited to
  • surrogate-based modeling and optimization methods including space mapping;
  • knowledge-based and tuning methodologies;
  • global optimization, evolutionary algorithms, particle swarm optimization, and so on;
  • multi-objective optimization;
  • adjoint-sensitivities for efficient gradient-based optimizers;
  • optimization techniques for nonlinear circuits;
  • software architectures for optimization-oriented design;
  • automated design optimization using EM simulators;
  • optimization for inverse EM problems;
  • neural network approaches; and
  • optimization for discrete problems.
Manuscripts for this Special Issue should adhere to the requirements for regular papers of the IJNM as specified in the Author Guidelines at http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1099-1204/homepage/ForAuthors.html
Potential contributors may contact the guest editor to determine the suitability of their contribution to the Special Issue. All manuscripts should be submitted via the IJNM's manuscript website http://mc.manuscriptcentral.com/ijnm, with a statement that they are intended for this Special Issue.

Manuscript submission deadline: January 31, 2015

Prof. Slawomir Koziel
Engineering Optimization and Modeling Center, 
School of Science and Engineering, 
Reykjavik University, Reykjavik, Iceland

May 4, 2014

[mos-ak] [Summary] Spring MOS-AK Workshop in London

 MOS-AK Compact Modeling Workshop
 London Metropolitan University
 March 28-29, 2014 London
 
The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, delivered its annual spring compact modeling workshop on March 28-29, 2014 at London Metropolitan University. The event received full sponsorship from leading industrial partners including Agilent Technologies, MOSIS Services and Tanner EDA. The technical MOS-AK program promoters included Eurotraining, IET, IEEE UKRI Section as well as EDA Solutions. More than 40 registered academic researchers and modeling engineers attended two sessions to hear 9 technical compact modeling presentations including the QUCS Tutorial by Prof. Mike Brinson.
 
The workshop summary has been posted thru the semiwiki.com blog and all the MOS-AK presentations are available for downloads here.
 
The MOS-AK/GSA Modeling Working Group is coordinating several upcoming modeling events to focus on the Verilog-A compact model standardization as well as open source circuit simulation tool developments: 
In the meantime, please also visit www.mos-ak.org where we will continue the discussions of all compact/SPICE modeling topics and its Verilog-A standardization.

--WG--V2014

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Apr 27, 2014

[mos-ak] CUSPICE: CUDA-accelerated NGSPICE release available immediately

 Recently, Francesco Lannutti, NGSPICE lead developer, has announced the CUSPICE: CUDA-accelerated NGSPICE release. The NVIDIA has recognised importance of the open source CAD/EDA tools and gave the permission to release CUSPICE as an integral part of the NGSPICE simulation platform. New NGSPICE extension is available immediately on the NGSPICE repository, in the branch named 'CUSPICE'. 

 At the moment only BSIM4v7, CAP, IND, ISRC, RES and VSRC device models are supported by the CUSPICE simulator. With broad acceptance of the NGSPICE simulation platform, we can expect other standard models and new extensions developed, soon. 

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Apr 21, 2014

[Abstracts Due Extended] 2014 NanoTech Workshop on Compact Modeling


 NanoTech Workshop on Compact Modeling Important Dates:
  • Late Poster Abstracts Due: Rolling Submissions - May 15
  • Notification: Rolling Notification Date
Authors of research submissions, upon acceptance, must register for the conference. [read more...]

Apr 17, 2014

Devices That You Definitely Will (and Just Might) Use: Emerging Transistor Technologies for the Near-and Long-Term

 WEDNESDAY June 04, 4:00pm - 6:00pm | Room 302 
 TRACK: EDA
 TOPIC AREA: EMERGING TECHNOLOGIES

 SPECIAL DAC SESSION 63: Devices That You Definitely Will (and Just Might) Use: Emerging Transistor Technologies for the Near-and Long-Term

Chair:  Michael Niemier; Univ. of Notre Dame, IN
Organizers:  Michael Niemier; Univ. of Notre Dame, IN
Xiaobo Sharon Hu; Univ. of Notre Dame, IN

Want to learn about the latest developments in FinFET-based processor design? What other transistor technologies might follow FinFETs and would they bring new design and modeling challenges? Come to this session to hear about both near- and long-term transistor technologies and their prospects for continuing Moore’s Law-based performance scaling trends. The session will begin with a discussion of FinFET technology; subsequent presentations will discuss tunnel transistors (TFETs) as well as other emerging FET technologies that could reenable voltage scaling. The session will conclude with a discussion of modeling efforts that consider the impact of new device technologies on von Neumann architectures as well as hybrid analog/digital circuits and architectures.

63.1 FinFET's and Their Implications for Design Now and in the Future

  • Speaker: Rob Aitken; ARM Ltd., San Jose, CA
    Greg Yeric; ARM Ltd., Austin, TX
    Brian Cline; ARM Ltd., Austin, TX
    Lucian Shifren; ARM Ltd., San Jose, CA

63.2 Emerging Devices for Logic: Can a Low-Power Switch Be Fast?

  • Speaker: Thomas Theis; IBM T.J. Watson Research Center, Yorktown Heights, NY

63.3 Energy Efficient Tunnel-FET Transistors for Beyond CMOS Logic

  • Speaker: Uygar Avci; Intel Corp., Portland, OR
    Daniel Morris; Intel Corp., Portland, OR
    Ian Young; Intel Corp., Hillsboro, OR

63.4 Steep Slope Devices: Enabling New Architectural Paradigms

  • Speaker: Vijaykrishnan Narayanan; Pennsylvania State Univ., State College, PA
    Karthik Swaminathan; Pennsylvania State Univ., State College, PA
    Huichu Liu; Pennsylvania State Univ., State College, PA
    Moon Seok Kim; Pennsylvania State Univ., State College, PA
    Xueqing Li; Pennsylvania State Univ., State College, PA
    Jack Sampson; Pennsylvania State Univ., University Park, PA