[paper] THz Measurements, Antennas, and Simulations

Fawad Sheikh 1, Andreas Prokscha 1, Johannes M. Eckhardt 2, Tobias Doeker 2, Naveed A. Abbasi 3, Jorge Gomez-Ponce 3,4, Benedikt Sievert 5, Jan Taro Svejda 5, Andreas Rennings 5, Jan Barowski 6, Christian Schulz 6, Ilona Rolfes 6, Daniel Erni 5, Andreas F. Molisch 3, Thomas Kürner 2, and Thomas Kaiser 1

THz Measurements, Antennas, and Simulations: From the Past to the Future

Invited Paper in IEEE Journal of Microwaves, vol. 3, no. 1, pp. 289-304, Jan. 2023

DOI: 10.1109/JMW.2022.3216210

1 Institute of Digital Signal Processing, UDE, Duisburg (D)

2 Institute for Communications Technology, TU Braunschweig (D)

3 Wireless Devices and Systems Group, University of Southern California, Los Angeles (USA) 
4 ESPOL, Facultad de Ingeniería en Electricidad y Computación, Guayaquil (EC)
5 ATE, University of Duisburg-Essen, and CENIDE Duisburg (D)
6 Institute of Microwave Systems, Ruhr University, Bochum (D)

Abstract: In recent years, terahertz (THz) systems have become an increasingly popular area of research thanks to their unique properties such as extremely high data rates towards Tb/s, submillimeter localization accuracy, high resolution remote sensing of materials, and remarkable advances in photonics and electronics technologies. This article traces the progress of the THz measurements, antennas and simulations, from historical milestones to the current state of research and provides an outlook on the remaining challenges.

FIG: Realized gain measurement of the integrated antenna prototype compared to the estimation of the corresponding equivalent circuit (EC) model in E- and H-plane at 290GHz (a)

and micrograph of the antenna prototype (b)

Acknowledgment: This work was supported in part by Deutsche Forschungsgemeinschaft for Projects M01, M02, M03, M04, C05, and S03, under Project 287022738 TRR 196, in part by the Ministry of Culture and Science of the State of North Rhine-Westphalia (MKW NRW) through Project terahertz.NRW, and in part by the Open Access Publication Fund of the University of Duisburg-Essen. The work of Jorge Gomez-Ponce was supported by Foreign Fulbright Ecuador SENESCYT Program. The work of Johannes M. Eckhardt, Tobias Doeker, and Thomas Kürner was supported in part by the Federal Ministry of Education and Research (BMBF), Germany, through 6G Research and Innovation Cluster 6G-RIC under Grant 16KISK031 and in part by German Research Foundation (DFG) under Grant FOR 2863, “Meteracom - Metrology for THz Communications.” The work of Jorge Gomez-Ponce, Naveed A. Abbasi, and Andreas F. Molisch was supported by SRC, DARPA, NSF, NIST, and Samsung Research America through ComSenTer Program. This work did not involve human subjects nor animals in its research.

[paper] SET and CMOS circuits

Tetsufumi Tanamoto¹, and Keiji Ono²

Simulations of hybrid charge-sensing single-electron-transistors and CMOS circuits

Appl. Phys. Lett. 119, 174002 (2021)

DOI: 10.1063/5.0068555

1Department of Information and Electronic Engineering, Teikyo University (J)
2Advanced Device Laboratory, RIKEN (J)

Abstract: Single-electron transistors (SETs) have been extensively used as charge sensors in many areas, such as quantum computations. In general, the signals of SETs are smaller than those of complementary metal–oxide–semiconductor (CMOS) devices, and many amplifying circuits are required to enlarge the SET signals. Instead of amplifying a single small output, we theoretically consider the amplification of pairs of SETs, such that one of the SETs is used as a reference. We simulate the two-stage amplification process of SETs and CMOS devices using a conventional SPICE (Simulation Program with Integrated Circuit Emphasis) circuit simulator. Implementing the pairs of SETs into CMOS circuits makes the integration of SETs more feasible because of direct signal transfer from the SET to the CMOS circuits.

Fig: (a) Six transistor SRAM cells applied in the second-stage amplification 

(b) Time-dependent voltage behaviors of the SRAM setup of L = 90 nm  

(c) Replotting of (b) for L = 65 nm.

MicroTec: Semiconductor Process and Device Simulator

Software Package for 2D Process and Device Simulation

Version 4.0 for Windows

User’s Manual

Publisher: Siborg Systems Inc

Editor: Michael S. Obrecht

MicroTec allows 2D silicon process modeling including implantation, diffusion and oxidation and 2D steady-state semiconductor device simulation like MOSFET, DMOS, JFET, BJT, IGBT, Schottky, photosensitive devices etc. Although MicroTec is significantly simplified compared to widely available commercial simulators, it nevertheless is a very powerful modeling tool for industrial semiconductor process/device design. In many instances MicroTec outperforms existing commercial tools and it is remarkably robust and easy-to-use.

FIG: MicroTec SibGraf GUI windows