Tetsufumi Tanamoto1, and Keiji Ono2
Simulations of hybrid charge-sensing single-electron-transistors and CMOS circuits
Appl. Phys. Lett. 119, 174002 (2021)
DOI: 10.1063/5.0068555
1Department of Information and Electronic Engineering, Teikyo University (J)
2Advanced Device Laboratory, RIKEN (J)
Abstract: Single-electron transistors (SETs) have been extensively used as charge sensors in many areas, such as quantum computations. In general, the signals of SETs are smaller than those of complementary metal–oxide–semiconductor (CMOS) devices, and many amplifying circuits are required to enlarge the SET signals. Instead of amplifying a single small output, we theoretically consider the amplification of pairs of SETs, such that one of the SETs is used as a reference. We simulate the two-stage amplification process of SETs and CMOS devices using a conventional SPICE (Simulation Program with Integrated Circuit Emphasis) circuit simulator. Implementing the pairs of SETs into CMOS circuits makes the integration of SETs more feasible because of direct signal transfer from the SET to the CMOS circuits.
Fig: (a) Six transistor SRAM cells applied in the second-stage amplification
(b) Time-dependent voltage behaviors of the SRAM setup of L = 90 nm
(c) Replotting of (b) for L = 65 nm.
