Showing posts with label degradations. Show all posts
Showing posts with label degradations. Show all posts

Sep 27, 2021

[paper] Degradations in LDMOS Transistors

Yen-Pu Chen1, Bikram K. Mahajan1, Dhanoop Varghese2, Srikanth Krishnan2, Vijay Reddy2
and Muhammad A. Alam1
Three-point I–V spectroscopy deconvolves region-specific degradations in LDMOS transistors
Appl. Phys. Lett. 119, 122102 (2021); 
DOI: 10.1063/5.0058477

1 Department of ECE, Purdue University, West Lafayette, Indiana 47906, USA
2 Texas Instruments Inc., Dallas, Texas 75043, USA

Abstract: Unlike traditional logic transistors, hot carrier degradation (HCD) in power transistors involves simultaneous and potentially correlated degradation in multiple regions. One must deconvolve and characterize the voltage- and temperature-dependence of these region-specific degradations to develop a predictive HCD model of power transistors. Unfortunately, power transistors' doping and geometrical complexities make it challenging to use traditional defect-profiling techniques, such as charge-pumping or gated-diode methods. This Letter uses a physics-based tandem-FET model of Laterally Diffused MOS (LDMOS) transistors to develop a “three-point I–V spectroscopy” technique that uses the time-evolution of three critical points of the measured I–V characteristics to extract mobility and threshold voltage degradations in the channel and drift regions. This innovative approach should generalize to other configurations of the LDMOS transistor as well.

Fig: The proposed tandem-FET compact model. The channel (ch) and the drift (dr) regions function individually as a MOSFET with different 𝑉th and dimensions. Three adjustable degradation parameters are 𝛥𝜇𝑐ℎ, 𝛥𝑉𝑐ℎth, and 𝛥𝜇𝑑𝑟.

Acknowledgements: Y.-P.C and B.K.M contributed equally to this work. The authors gratefully acknowledge the access to the characterization facilities at Birck Nanotechnology Center, Purdue University, for the results presented in this article.