[review] TCAD Simulations of Semiconductor Piezoresistance

Takaya Sugiura, Kazunori Matsuda*, Nobuhiko Nakano

Review: Numerical Simulations of Semiconductor Piezoresistance for Computer-Aided Designs

in IEEE J-EDS, vol. 11, pp. 325-336, 2023

DOI: 10.1109/JEDS.2023.3281866

  Department of Electronics and Electrical Engineering, Keio University, Yokohama, Kanagawa, Japan

* Division of Electrical, Electronic and Infocommunications Engineering, Osaka University, Suita, Japan

Abstract: The field of piezoresistance has mainly advanced through experimental research; however, the improved accuracy of simulations and the emergence of new materials have increased the importance of simulations in this field. This review discusses the methods and current topics related to simulations of piezoresistive devices. Advancing simulation modeling will facilitate the computer-aided design of piezoresistive devices, and this review introduces the means of establishing these models by discussing the current studies on simulations and calculations in this field. Two simulation methods currently exist namely, device simulations and first-principles theoretical analysis. This review focuses on numerical simulation approaches for modeling of the piezoresistive effect using the multiphysics simulations of the mechanical and electrical behaviors of piezoresistive materials.

FIG: Basic simulation flow for studies on semiconductor piezoresistors.

[paper] Vertical Junction-Less Nanowire FETs

C. Maneux (University of Bordeaux), C. Mukherjee (CNRS), M. Deng (University of Bordeaux), G. Larrieu (CNRS), Y. WANG, B. Wesling, and H. Rezgui (University of Bordeaux)

Strategies for Characterization and Parameter Extraction of Vertical Junction-Less Nanowire FETs Dedicated to Design Technology Co-Optimization

H02-1863 (Invited) at 243rd ECS Meeting and SOFC-XVIII 

Boston, MA, May 29 - June 2, 2023

Abstract: In the era of emerging computing paradigms and artificial neural networks, hardware and functionality requirements are in the surge. In order to meet low power and latency criteria, new architectures for in-memory computing are being explored as alternatives to traditional von Neumann machines, which requires technological breakthrough at the semiconductor device level such as vertical gate-all-around junctionless nanowire field effect transistors (VNWFET), that can address many process challenges such as downscaling, short-channel effects, compactness and electrostatic control. Its integration in the mainstream design flow is not straightforward and requires design technology co-optimization (DTCO) at an early stage. This invited paper explores strategies for accurate characterization and parameter extraction of the VNWFETs to feed the DTCO compact models

Fig: Final verification using full 3D multiphysics device thermal simulation, accounting for both ballistic and diffusive heat flux

[paper] FDSOI Threshold Voltage Model

Hung-Chi Han1, (Student, IEEE), Zhixing Zhao2, Steffen Lehmann2,

Edoardo Charbon1, (Fellow, IEEE), and Christian Enz1 (Life Fellow, IEEE)

Novel Approach to FDSOI Threshold Voltage Model Validated at Cryogenic Temperatures

in IEEE Access, DOI: 10.1109/ACCESS.2023.3283298

1 Ecole Polytechnique Fédérale de Lausanne (EPFL), 2000 Neuchâtel, Switzerland
2 GlobalFoundries, 01109 Dresden, Germany

Abstract: The paper presents a novel approach to to the modeling of the back-gate dependence of the threshold voltage of Fully Depleted Silicon-On-Insulator (FDSOI) MOSFETs down to cryogenic temperatures by using slope factors with a gate coupling effect. The FDSOI technology is well-known for its capability to modulate the threshold voltage efficiently by the back-gate voltage. The proposed model analytically demonstrates the threshold voltage as a function of the back-gate voltage without the pre-defined threshold condition, and it requires only a calibration point, i.e., a threshold voltage with the corresponding back-gate voltage, front- and back-gate slope factors, and work functions of front and back gates. The model has been validated over a wide range of the back-gate voltages at room temperature and down to 3 K. It is suitable for optimizing low-power circuits at cryogenic temperatures for quantum computing applications

FIG: Room temperature back-gate coefficient η versus VT−VB for an n-type conventional well (RVT) FDSOI FET with 1 µm of gate length and width. The θ=0 happens at VT−VB = −0.63V due to −0.63V of the front-back gate work function difference 

Acknowledgment: The authors would like to thank Claudia Kretzschmar from GlobalFoundries Germany and GlobalFoundries University Partnership Program for providing 22 FDX® test structures and support. Hung-Chi Han would like to thank Davide Braga from Fermi National Accelerator Laboratory for his valuable support. This project has received funding from the European Union’s Horizon 2020 Research & Innovation Program under grant agreement No. 871764. SEQUENCE.

[paper] Vacuum Electron Devices

R. Lawrence Ives, Life Senior Member, IEEE

Advanced Fabrication of Vacuum Electron Devices

(Invited Paper)

IEEE TED, Vol. 70, No. 6, June 2023

DOI: 10.1109/TED.2023.3268629

Abstract: RF source scientist and engineers continuously push the envelope with new designs, striving for improved performance with higher efficiency, higher frequency, greater bandwidth, increased gain, smaller size, lower voltage, and myriad other parameters required for ever more demanding applications. Invariably, it becomes more challenging to achieve the required fabrication and assembly performance with increasing complexity and precision. This publication reviews recent development on advanced fabrication technologies and describes the current state of the art in machining, assembly, and alignment capabilities.

FIG: Assembled 11.4-GHz accelerating structure assembled with elastic averaging

Acknowledgment: Several people assisted with this article, and the author would like to acknowledge their contributions. These include Jeff Herman at Ron Witherspoon, Inc., Colin Joye at the Naval Research Laboratory, Daniel Busbaher at 3M Technical Ceramics, Diana Gamzina at Elvespeed, Emma Snively at SLAC National Accelerator Laboratory, and Philipp Borchard at Dymenso. The author would like to thank RWI for access to their facilities to see their micro-CNC and software capabilities in operation.

[paper] Microchips for Memristive Applications

Kaichen Zhu, Sebastian Pazos, Fernando Aguirre, Yaqing Shen, Yue Yuan, Wenwen Zheng, Osamah Alharbi, Marco A. Villena, Bin Fang, Xinyi Li, Alessandro Milozzi, Matteo Farronato, Miguel Muñoz-Rojo, Tao Wang, Ren Li, Hossein Fariborzi, Juan B. Roldan, Guenther Benstetter, Xixiang Zhang, Husam N. Alshareef, Tibor Grasser, Huaqiang Wu, Daniele Ielmini & Mario Lanza 

Hybrid 2D–CMOS microchips for memristive applications

Nature 618, 57–62 (2023)

DOI: 10.1038/s41586-023-05973-1

Abstract: Exploiting the excellent electronic properties of two-dimensional (2D) materials to fabricate advanced electronic circuits is a major goal for the semiconductor industry1,2. However, most studies in this field have been limited to the fabrication and characterization of isolated large (more than 1 µm2) devices on unfunctional SiO2–Si substrates. Some studies have integrated monolayer graphene on silicon microchips as a large-area (more than 500 µm2) interconnection3 and as a channel of large transistors (roughly 16.5 µm2) (refs. 4,5), but in all cases the integration density was low, no computation was demonstrated and manipulating monolayer 2D materials was challenging because native pinholes and cracks during transfer increase variability and reduce yield. Here, we present the fabrication of high-integration-density 2D–CMOS hybrid microchips for memristive applications—CMOS stands for complementary metal–oxide–semiconductor. We transfer a sheet of multilayer hexagonal boron nitride onto the back-end-of-line interconnections of silicon microchips containing CMOS transistors of the 180 nm node, and finalize the circuits by patterning the top electrodes and interconnections. The CMOS transistors provide outstanding control over the currents across the hexagonal boron nitride memristors, which allows us to achieve endurances of roughly 5 million cycles in memristors as small as 0.053 µm2. We demonstrate in-memory computation by constructing logic gates, and measure spike-timing dependent plasticity signals that are suitable for the implementation of spiking neural networks. The high performance and the relatively-high technology readiness level achieved represent a notable advance towards the integration of 2D materials in microelectronic products and memristive applications.

FIG: Structure of the considered SNN. Each MNIST image is reshaped as a 784x1 column vector, and the intensity of the pixels is encoded in terms of the firing frequency of the input neurons. The only trainable synapses are those connecting the input layer with the excitatory layer, and they are modelled with the STDP characteristic of the CMOS-h-BN based 1T1M cells. The learning is unsupervised, and the neurons are labelled only after the training. These label-neuron assignments are then feed to the decision block altogether with the firing patterns of the neurons, to infer the class of the image presented in the input. 

Acknowledgements: This work has been supported by the Ministry of Science and Technology of China (grant nos. 2019YFE0124200 and 2018YFE0100800), the National Natural Science Foundation of China (grant no. 61874075) and the Baseline funding scheme of the King Abdullah University of Science and Technology.