[mos-ak] [Final Program] Spring MOS-AK/GSA Workshop in Munich; April 11-12, 2013

Together with the workshop host, Prof. Dr. Doris Schmitt-Landsiedel, Lehrstuhl fur Technische Elektronik, TUM and Extended MOS-AK/GSA TPC Committee and the workshop sponsors MunEDA and Tanner EDA as well as the IEEE EDS Chapter Germany, the technical program cosponsor, we have pleasure to invite to the spring MOS-AK/GSA Workshop in Munich 

Venue:

Lehrstuhl fur Technische Elektronik

Room: 5325, 5th floor <http://www.lte.ei.tum.de/index.html>

Technische Universitat Munchen 

Arcisstr. 21 D-80333 Munchen

Registration: free on-line registration

MOS-AK/GSA Workshop Agenda

<http://www.mos-ak.org/munich_2013/>

April 11	Thursday, Afternoon Session
13:00 - 16:00	Oral presentations
	Welcome and Workshop Opening Wladek Grabinski; MOS-AK
	Statistical modeling with backward propagation of variance (BPV) and covariance equations Klaus-Willi Pieper and Elmar Gondro; Infineon Technologies
	Circuit Sizing: Corner Models Challenges & Applications Matthias Sylvester; MunEDA (D)
	Compact Modeling Activities in The Framework of the EU-Funded "COMON" Project Benjamin Iñiguez; URV, Tarragona (SP)
	Effective Device Modeling And Verification Tools Ingo Nickeleit; Agilent Technologies
16:00 - 17:00	Software/Hardware Demos
	MunEDA Framework Applications Tanner TSpice Verilog-A Agilent B1505A Power Device Analyzer / Curve Tracer
	Networking Evening Event
April 12	Friday, Sessions
9:00 - 12:00	Morning Oral Presentations
	Institute for Technical Electronics (LTE) Presentation  Prof. Dr. rer. nat. Doris Schmitt-Landsiedel, LTE, TUM (D)
	STEEPER: Tunnel Field Effect Transistors (TFETs) Technology, Devices and Applications  Thomas Schulz and Reinhard Mahnkopf, Intel, IMC, (D)
	Current and Future Challenges for TCAD Christoph Jungemann and Christoph Zimmermann; RWTH Aachen University (D)
	Advances in Verilog-A Compact Semiconductor Device Modeling with Qucs/QucsStudio Mike Brinson; London Metropolitan University, London, UK
12:00 - 13:00	Lunch
13:00 - 16:00	Afternoon Oral Presentations
	FDSOI Devices Bentchmarking Bich-Yen Nguyen; SOITEC (F)
	COMON: SOI Multigate Devices Modeling Alexander Kloes; THM (D)
	COMON: FinFET Modeling Activities  Udit Monga; Intel, IMC, (D)
	COMON: HV MOS Devices Modeling Matthias Bucher; TUC, (GR)
	End of the Workshop

Committee: Extended MOS-AK/GSA Committee

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Call for IJNM Papers: Modeling of high-frequency silicon transistors

Silicon transistors (STs) have been the workhorse of the electronics industry ever since its inception. Although STs historically have been used primarily in digital and low-frequency analog applications, they increasingly are being adopted for high-frequency analog purposes as well. This trend is fueled by the introduction of new fabrication methods, novel materials, and transistor architectures that permit aggressive downscaling into the nanometer regime. Along these lines, considerable attention currently is being devoted to the FinFET, which is an innovative multiple-gate field effect transistor offering the important advantage of being compatible with conventional planar CMOS technology.

Modeling and simulation are indispensable in the development of high-frequency STs. Indeed, ST models and simulations provide indispensable feedback for improving device fabrication processes and serve as a valuable tool for optimizing circuit designs. Unfortunately, the predictive power of modeling and simulation techniques for STs for digital and low-frequency applications oftentimes diminishes when applied to high-frequency analog STs. For modeling and simulation methods to drive the development of high-frequency ST technology, they must adapt as well. 

The purpose of this Special Issue is to publish high-quality contributions addressing the modeling and simulation of high-frequency STs. A wide range of topics will be covered, ranging from bipolar to ?eld effect transistors and from linear to noise and non-linear models. Although the main focus of the Special Issue will be the extraction of high-frequency models, papers addressing other aspects of ST modeling will be considered as well. This issue will contain both invited and contributed papers. Manuscripts for this Special Issue should adhere to the requirements for regular papers of the IJNM as specified in the Author Guidelines at http://onlinelibrary.wiley.com/journal/10.1002/ (ISSN)1099-1204/homepage/ForAuthors.html.

Potential contributors may contact the Guest Editors to determine the suitability of their contribution to the Special Issue. All manuscripts should be submitted via the IJNM’s manuscript website http://mc.manuscriptcentral.com/ijnm, with a statement that they are intended for this Special Issue.

Guest Editors:

• Dr. Giovanni Crupi
  University of Messina, Italy
  E-mail: crupig@unime.it
• Prof. Dominique Schreurs
  University of Leuven, Belgium
  E-mail: dominique.schreurs@esat.kuleuven.be
• Prof. Alina Caddemi
  University of Messina, Italy
  E-mail: acaddemi@unime.it

Manuscript submission deadline: April 30, 2013

[mos-ak] [2nd announcement] Spring MOS-AK/GSA Workshop in Munich; April 11-12, 2013

Together with the workshop host, Prof. Dr. Doris Schmitt-Landsiedel, Lehrstuhl fur Technische Elektronik, TUM and Extended MOS-AK/GSA TPC Committee and the workshop sponsors MunEDA and Tanner EDA, we have pleasure to invite to the spring MOS-AK/GSA Workshop in Munich <http://www.mos-ak.org/munich_2013/>

Venue:

Lehrstuhl fur Technische Elektronik

Room: 5325, 5th floor <http://www.lte.ei.tum.de/index.html>

Technische Universitat Munchen 

Arcisstr. 21 D-80333 Munchen

Important Dates:

• Call for Papers - Jan. 2013
  
• 2nd Announcement - March 2013
  
• Final Workshop Program - March, 2013
  
• MOS-AK/GSA Workshop - April 11-12, 2013

R&D topics to be covered include the following:

• Advances in semiconductor technologies and processing
  
• Compact Modeling (CM) of the electron devices
  
• Verilog-A language for CM standardization
  
• New CM techniques and extraction software
  
• CM of passive, active, sensors and actuators
  
• Emerging Devices, CMOS and SOI-based memory cells
  
• Microwave, RF device modeling, high voltage device modeling
  
• Nanoscale CMOS devices and circuits
  
• Technology R&D, DFY, DFT and IC Designs
  
• Foundry/Fabless Interface Strategies

Postworkshop publications;

selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of Numerical Modelling: Electronic Networks, Devices and Fields

Extended MOS-AK/GSA Committee

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DEVSIM is now open source

Juan Sanches of Devsim LLC (Austin, Texas) announced:

DEVSIM is now open source 

The source code for my device simulation software, DEVSIM, is now available for download. The core engine is released under the LGPL 3.0. I hope this software will be useful to the TCAD community and it is available for download from github:

https://github.com/devsim/devsim?goback=.gde_164417_member_223659152

Great. Looks very interesting. A lot of good code. Anyone here by chance has any experience with it?

NANO 2013

Symposium on Nanostructured Materials to be held May 21-22, 2013 at the University of Rzeszow, Poland. The Symposium will be a major event during the grand opening of the Center for Microelectronics and Nanotechnology. This conference is devoted to the current trends in research on layer-structured materials and one-dimensional nanomaterials. Emphasis will be placed on the state-of-the-art metrology for detecting defects and impurities using modern TEM, SIMS, and Nano-Raman methods etc. Specific areas of interest include:

• MBE technology, 
• nanopatterning, 
• nanolithography, 
• photolithography and electron lithography for the production of integrated circuits, 
• magneto-transport at low temperatures, 
• optical properties of nanostructures, 
• interaction between academic and industrial research
  (instrument manufacture, IC and optoelectronics industry, and materials suppliers).

[read more...]