RC and RL circuits and smartphones

Marciano Santamaría Lezcano1 E S Cruz de Gracia2, Lucio Strazzabosco Dorneles3 

and Noriel Correa1

Frequency effect on reactance in RC and RL circuits - a smartphone approach

Phys. Educ. 60 (2025) 035033 (8pp) 

DOI: 10.1088/1361-6552/adc8ec

1 Universidad de Panamá, Departamento de Física, Centro de Investigación con Técnicas Nucleares, Panama City, Panama
2 Universidad Tecnológica de Panama, Centro Regional de Veraguas, Veraguas, Panama
3 Universidade Federal de Santa Maria, Santa Maria, RS, Brazil

emails: evgeni.cruz@utp.ac.pa, marciano.santamaria@up.ac.pa, lucio.dorneles@ufsm.br and noriel.correa@up.ac.pa

Abstract: This paper presents a new and successful methodology for determining the frequency effect on capacitive and inductive reactance in RC and RL series circuits. The key feature in our approach is the practical use of a smartphone as a signal generator and an oscilloscope in alternating current circuits. By generating and visualising the signal using free software applications, we could observe the capacitor's and the inductor's response to frequency variations between 0.1 and 5.0 kHz. The experimental data, analysed within the theoretical capacitive and inductive reactance model, shows excellent agreement with the expected values, instilling confidence in the reliability and feasibility of our methodology. This alignment between experimental and theoretical data not only underscores the potential use of smartphone technology in capacitive and inductive reactance studies but also highlights the practicality of our approach to experimental analysis in science and engineering.

FIG: The connection diagram of (a) RC and (b) RL circuits

shows smartphones working as signal generators and oscilloscopes.

Data availability statement: All data that support the findings of this study are included within the article (and any supplementary files).

Acknowledgments: The authors, M. Santamaría and N. Correa would like to thank the Development Bank of Latin America and the Caribbean (CAF) for financially supporting the Renovation Program of the Faculty of Natural and Exact Sciences and Technology of the University of Panama, which includes the acquisition of instruments used in this research. E S Cruz de Gracia, an SNI member, thanks the Secretaria Nacional de Ciencia, Tecnología e Innovación (SENACYT) for its support. Finally, L.S. Dorneles acknowledges support from CNPq Grant 308277/2021-0.

[paper] Avalanche Multiplication in SiGe HBTs

Zhang, Huaiyuan, Guofu Niu, Andries J. Scholten, and Marnix B. Willemsen

"Avalanche Multiplication Factor Modeling and Extraction at High Currents in SiGe HBTs"

IEEE Transactions on Electron Devices (2025)

DOI: 10.1109/TED.2025.3558114

1. Auburn University, Auburn, AL, USA

2. NXP, Eindhoven, The Netherlands

Abstract: A new compact model and an extraction method for avalanche multiplication factor (M-1) at high currents are proposed. At a fixed collector–base (CB) voltage (VCB), M-1 first decreases with increasing emitter current (IE) and then increases at higher currents when the Kirk effect occurs. Different forced-IE M-1 extraction techniques are evaluated, including a new compact modeling-based M-1 extraction technique that accurately captures the Early effect, the Kirk effect, and self-heating. The model is implemented in a development version of MEXTRAM and demonstrated experimentally to model both the current and bias dependence of M-1 and base current (IB). 

FIG: Simplified dc equivalent circuit of a transistor under forced IE,VCB 

and  fT(IE) meas/sim up to 150 mA at VCB = 1, 2, and 3 V (b)

Acknowledgment: The authors wish to acknowledge the support of the Compact Model Coalition (CMC).

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hashtag

[C4P] Micro-Nano 2025

International Conference on Micro- and Nanoelectronics, Nanotechnology and MEMS (MicroNano 2025)

https://2025.micro-nano.gr/

This annual Micro-Nano 2025 conference is organized by the Micro&Nano Scientific Society of Greece and aims to connect people from academia, research and industry, so as to stimulate discussions on the latest scientific achievements and to further promote micro- and nanotechnologies. The conference is held every time in a different city all around Greece, with the most recent one realized in Lemnos (2024). This year's Conference will be held on the island of Crete and is co-organized with the Technical University of Crete.

ABSTRACT SUBMISSION

• Conference Dates: November 6-9, 2025
• Submission Opens: will be announced
• Abstract Submission Final Deadline: will be announced
• Peer reviewing will follow immediately after submission.

[paper] Compact OTM-RRAM Characterization Platform

Max Uhlmann, Milosz Krysik, Jianan Wen, Max Frohberg, Andrea Baroni, Keerthi Dorai Swamy Reddy, 

Eduardo Pérez, Philip Ostrovskyy, Krzysztof Piotrowski, Corrado Carta, Christian Wenger, 

and Gerhard Kahmen

A Compact One-Transistor-Multiple-RRAM Characterization Platform

IEEE Transactions on Circuits and Systems I: Regular Papers (2025)

DOI: 10.1109/TCSI.2025.3555234

1. IHP GmbH Frankfurt (Oder) (D)

2. Faculty of Mathematics, Computer Science, Physics, Electrical Engineering and Information Technology, TU Brandenburg (D)

3. Institute of High-Frequency and Semiconductor System Technologies, TU Berlin (D)

Abstract: Emerging non-volatile memories (eNVMs) such as resistive random-access memory (RRAM) offer an alternative solution compared to standard CMOS technologies for implementation of in-memory computing (IMC) units used in artificial neural network (ANN) applications. Existing measurement equipment for device characterisation and programming of such eNVMs are usually bulky and expensive. In this work, we present a compact size characterization platform for RRAM devices, including a custom programming unit IC that occupies less than 1 mm2 of silicon area. Our platform is capable of testing one-transistor-one-RRAM (1T1R) as well as one-transistor-multiple-RRAM (1TNR) cells. Thus, to the best knowledge of the authors, this is the first demonstration of an integrated programming interface for 1TNR cells. The 1T2R IMC cells were fabricated in the IHP's 130 nm BiCMOS technology and, in combination with other parts of the platform, are able to provide more synaptic weight resolution for ANN model applications while simultaneously decreasing the energy consumption by 50%. The platform can generate programming voltage pulses with a 3.3 mV accuracy. Using the incremental step pulse with verify algorithm (ISPVA) we achieve 5 non-overlapping resistive states per 1T1R device. Based on those 1T1R base states we measure 15 resulting state combinations in the 1T2R cells.

FIG. The GDSII layout, schematic (a) and transmission electron microscopic (TEM) cross section image (b) of a 1T1R structure in IHP's 130 nm BiCMOS technology, with its material stack (c) and resitive switching mechanism principle (d).

Acknowledgement: This work was supported by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) under Project 434434223–SFB 1461