Abstract: Emerging non-volatile memories (eNVMs) such as resistive random-access memory (RRAM) offer an alternative solution compared to standard CMOS technologies for implementation of in-memory computing (IMC) units used in artificial neural network (ANN) applications. Existing measurement equipment for device characterisation and programming of such eNVMs are usually bulky and expensive. In this work, we present a compact size characterization platform for RRAM devices, including a custom programming unit IC that occupies less than 1 mm2 of silicon area. Our platform is capable of testing one-transistor-one-RRAM (1T1R) as well as one-transistor-multiple-RRAM (1TNR) cells. Thus, to the best knowledge of the authors, this is the first demonstration of an integrated programming interface for 1TNR cells. The 1T2R IMC cells were fabricated in the IHP's 130 nm BiCMOS technology and, in combination with other parts of the platform, are able to provide more synaptic weight resolution for ANN model applications while simultaneously decreasing the energy consumption by 50%. The platform can generate programming voltage pulses with a 3.3 mV accuracy. Using the incremental step pulse with verify algorithm (ISPVA) we achieve 5 non-overlapping resistive states per 1T1R device. Based on those 1T1R base states we measure 15 resulting state combinations in the 1T2R cells.
Apr 24, 2025
[paper] Compact OTM-RRAM Characterization Platform
Max Uhlmann, Milosz Krysik, Jianan Wen, Max Frohberg, Andrea Baroni, Keerthi Dorai Swamy Reddy,
Eduardo Pérez, Philip Ostrovskyy, Krzysztof Piotrowski, Corrado Carta, Christian Wenger,
and Gerhard Kahmen
A Compact One-Transistor-Multiple-RRAM Characterization Platform
IEEE Transactions on Circuits and Systems I: Regular Papers (2025)
DOI: 10.1109/TCSI.2025.3555234
1. IHP GmbH Frankfurt (Oder) (D)
2. Faculty of Mathematics, Computer Science, Physics, Electrical Engineering and Information Technology, TU Brandenburg (D)
3. Institute of High-Frequency and Semiconductor System Technologies, TU Berlin (D)
FIG. The GDSII layout, schematic (a) and transmission electron microscopic (TEM) cross section image (b) of a 1T1R structure in IHP's 130 nm BiCMOS technology, with its material stack (c) and resitive switching mechanism principle (d).
Acknowledgement: This work was supported by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) under Project 434434223–SFB 1461
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