[paper] Flexible Megahertz Organic Transistors

Jakob Leise^1,4, Jakob Pruefer^1,4, Ghader Darbandy¹, Aristeidis Nikolaou^1,4, Michele Giorgio², Mario Caironi², Ute Zschieschang³, Hagen Klauk³, Alexander Kloes¹, Benjamin Iñiguez⁴

and James W. Borchert⁵

Flexible megahertz organic transistors and the critical role of the device geometry on their dynamic performance

Journal of Applied Physics 130, 125501 (2021); 

DOI: 10.1063/5.0062146

  
1NanoP, TH Mittelhessen University of Applied Sciences, Gießen 35390, Germany
2Center for Nano Science and Technology @PoliMi, Istituto Italiano di Tecnologia, Milano 20133, Italy
3Max Planck Institute for Solid State Research, Stuttgart 70569, Germany
4DEEA, Uniersitat Rovira i Virgili, Tarragona 43007, Spain
5Georg August University of Goettingen, Goettingen 37077, Germany
  

Abstract: The development of organic thin-film transistors (TFTs) for high-frequency applications requires a detailed understanding of the intrinsic and extrinsic factors that influence their dynamic performance. This includes a wide range of properties, such as the device architecture, the contact resistance, parasitic capacitances, and intentional or unintentional asymmetries of the gate-to-contact overlaps. Here, we present a comprehensive analysis of the dynamic characteristics of the highest-performing flexible organic TFTs reported to date. For this purpose, we have developed the first compact model that provides a complete and accurate closed-form description of the frequency-dependent small-signal gain of organic field-effect transistors. The model properly accounts for all relevant secondary effects, such as the contact resistance, fringe capacitances, the subthreshold regime, charge traps, and non-quasistatic effects. We have analyzed the frequency behavior of low-voltage organic transistors fabricated in both coplanar and staggered device architectures on flexible plastic substrates. We show through S-parameter measurements that coplanar transistors yield more ideal small-signal characteristics with only a weak dependence on the overlap asymmetry. In contrast, the high-frequency behavior of staggered transistors suffers from a more pronounced dependence on the asymmetry. Using our advanced compact model, we elucidate the factors influencing the frequency-dependent small-signal gain and find that even though coplanar transistors have larger capacitances than staggered transistors, they benefit from substantially larger transconductances, which is the main reason for their superior dynamic performance.

Fig: Schematic cross-section of a top-contact (TC) organic TFT. Here, the semiconductor layer separates the source and drain contacts from the gate dielectric and thus from the gate-field-induced charge-carrier channel; hence, these transistors are also referred to as staggered TFTs. The overlap regions are assumed as a series connection of two capacitances. However, when the organic semiconductor (OSC) is operated in accumulation, the accumulation charges change the behavior of the series connection. The charge density at the source end of the channel is assumed to be found in the entire gate-to-source overlap region. 

Acknowledgments: The authors thankfully acknowledge funding for this project from the German Federal Ministry of Education and Research (“SOMOFLEX,” No. 13FH015IX6) and EU H2020 RISE (“DOMINO,” No. 645760), and the German Research Foundation (DFG) under Grant Nos. KL 1042/9-2, KL 2223/6-1, and KL 2223/6-2 (SPP FFlexCom). The authors would like

Memory for Synaptic Operations

Md. Hasan Raza Ansari, Udaya Mohanan Kannan and Seongjae Cho 

Core-Shell Dual-Gate Nanowire Charge-Trap Memory

for Synaptic Operations for Neuromorphic Applications

Nanomaterials 2021, 11, 1773

DOI 10.3390/nano11071773

 
Graduate School of IT Convergence Engineering, Gachon University, Seongnam 13120, Korea;
 

Abstract: This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depression (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural network, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping the holes from the nitride layer shows the LTD operation. Furthermore, linearity and symmetry in conductance are achieved through optimal device design and biases. In a system-level simulation, with CSDG nanowire transistor a recognition accuracy of up to 92.28% is obtained in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. Complementary metal-oxide-semiconductor (CMOS) compatibility and high recognition accuracy makes the CSDG nanowire transistor a promising candidate for the implementation of neuromorphic hardware.

Fig: Schematic representation of biological synapse and 2D representation of CSDG nanowire transistor for artificial synapse device.

Acknowledgement: This research was supported by the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (MSIT) (No. 2016M3A7B4910348, Nano-Material Technology Development Program, 50%) and was partly supported by Institute of Information & Communications Technology Planning & Evaluation (IITP) grant funded by the Korean government (MSIT) (No. 2020-0-01294, Development of IoT based edge computing ultra-low power artificial intelligent processor, 50%).

[see also] M. H. R. Ansari, S. Cho, J.-H. Lee, and B.-G. Park, “Core-Shell Dual-Gate Nanowire Memory as a Synaptic Device for Neuromorphic Application,” IEEE Journal of the Electron Devices Society, pp. 1–1, 2021. DOI: 10.1109/JEDS.2021.3111343

[paper] Organic Semiconductor Devices

D. Oussalah^1,2, R. Clerc², J. Baylet¹, R. Paquet¹, C. Sésé¹, C. Laugier¹, B. Racine¹

and J. Vaillant¹

On the minimum thickness of doped electron/hole transport layers 

in organic semiconductor devices 

Journal of Applied Physics 130, 125502 (2021);

DOI: 10.1063/5.0060429

  
1Université Grenoble Alpes, CEA, Leti, Grenoble 38000, France
2Université de Lyon, UJM-Saint-Etienne, CNRS, IOGS, Lab. Hubert Curien, UMR5516 St-Etienne, France

  

Abstract: Doped hole (respectively electron) transport layers [HTLs (respectively ETLs)] are commonly used in evaporated organic devices to achieve high work function hole contact (respectively low work function electron contact) in organic LEDs to inject large current, in solar cells to increase the open circuit voltage, and in photodetectors to minimize the dark current. However, optimization of the HTL thickness results from a delicate trade-off. Indeed, on the one hand, to minimize the impact of HTLs on light propagation and series resistance effects, it is commonly admitted that HTLs must be kept as thin as possible. In this work, a model, validated by drift and diffusion simulations, has shown that, depending of the doping level, a minimum thickness between 10 and 20 nm was needed to prevent the transport layer work function from degradation due to field effects. Experiments have been performed on template p-only devices featuring a single HTL of various thicknesses and doping, confirming the validity of the model. Finally, simulations have been performed on a p-i-n device featuring both HTL and ETL. These results constitute precious indications for the design of efficient evaporated organic LEDs, solar cells, or photodetectors.

Fig: Image of a top view of the 200 mm silicon wafer processed to realize TiN/STTB:F4TCNQ/ZnPc:C60/Ag devices.

[paper] Enhancing multi-functionality of reconfigurable transistors

Y.V. Bhuvaneshwari and Abhinav Kranti

Enhancing multi-functionality of reconfigurable transistors 

by implementing high retention capacitorless dynamic memory

Semicond. Sci. Technol. 36 (2021) 115003 (9pp)

DOI:10.1088/1361-6641/ac2315

Low Power Nanoelectronics Research Group, Department of Electrical Engineering, Indian Institute of Technology Indore, Simrol, Indore 453552, Madhya Pradesh, India

Abstract: A key indicator of multi-functional attributes of a transistor is technological competitiveness vis-a-vis existing architectures. Apart from the well-known logic circuit implementation through reconfigurable field effect transistors (RFETs), this work showcases feasible memory operation by realising capacitorless (1T) dynamic random access memory (DRAM). The memory operation in RFET is achieved through back control gate which creates an electrostatic potential well to store holes. Due to the inherent features of RFET architecture a wider and deeper potential well results in a significantly high retention time (RT) of 2.3s at 85C for a total length of 90 nm. Apart from high retention, RFET based 1T-DRAM exhibits a low write time of ∼2ns, sense margin (SM) of ∼76µA/µm and a high current ratio (CR) of ∼105. Benchmarking the performance metrics against previously published results indicates competitiveness for RT in terms of total length, storage volume and high temperature operation. Critical insights aiding competitive multi-functional behaviour through 1T-DRAM highlights the possible implementation of logic and memory blocks with RFETs.

Fig: Schematic diagram of a planar DG RFET with two PGs and one CG. The CG length (Lcg) and PG length (Lpg) were varied from 100 to 10 nm, spacing (Lgap) between CG and PG was varied from 40 to 30 nm, and the undoped film of thickness (Tsi) was varied from 9 to 12 nm. The thickness of HfO2 layer (THfO2) was kept constant at 4 nm. A midgap workfunction (φm=4.7 eV) was used for polarity and CGs. Holes are stored at the back surface (y=Tsi) in the potential well created due to the application of a negative voltage at the back CG.

Acknowledgments: This work was supported by the Science and Engineering Research Board (SERB), Department of Science and Technology (DST), Government of India, under GrantCRG/2019/002937.

[@iannak1] The size of the investment needed for one single new state-of-art fab is way beyond the Semiconductor Industry support plans of all European governments #semi #fab #chip #wafer #investment #EU https://t.co/aj6fnXB4r8

[@iannak1] The size of the investment needed for one single new state-of-art fab is way beyond the Semiconductor Industry support plans of all European governments #semi #fab #chip #wafer #investment #EU https://t.co/aj6fnXB4r8

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