Compact DC Modeling of Organic Field-Effect Transistors: Review and Perspectives

In spite of impressive improvements achieved for organic field-effect transistors (OFETs), there is still a lack of theoretical understanding of their behaviors. Furthermore, it is challenging to develop a universal model that would cover a huge variety of materials and device structures available for state-of-the-art OFETs. Nonetheless, currently there is a strong need for specific OFET compact models when device-to-system integration is an important issue. We briefly describe the most fundamental characters of organic semiconductors and OFETs, which set the bottom line dictating the requirement of an original model different from that of conventional inorganic devices. Along with an introduction to the principles of compact modeling for circuit simulation, a comparative analysis of the reported models is presented with an emphasis on their primary assumptions and applicability aspects. Critical points for advancing OFET compact models are discussed in consideration of the recent understanding of device physics.

[1] Kim, C.-H.; Bonnassieux, Y.; Horowitz, G., "Compact DC Modeling of Organic Field-Effect Transistors: Review and Perspectives," Electron Devices, IEEE Transactions on , vol.61, no.2, pp.278,287, Feb. 2014
doi: 10.1109/TED.2013.2281054
URL

[Final Program] EUROSOI 2014, Tarragona, Catalonia, Spain; January 27-29, 2014

The 10th Workshop of the Thematic Network
on Silicon on Insulator Technology, Devices and Circuits 

(EUROSOI 2014) 

Tarragona, Catalonia, Spain 

January 27-29, 2014 

The EUROSOI Workshop is an international forum to promote interaction and exchangesbetween research groups and industrial partners involved in SOI activities all over the world. Following the lively experience of the previous meetings in Granada (2005), Grenoble (2006), Leuven (2007), Cork (2008), Gšteborg (2009), Grenoble (2010), Granada (2011), Montpellier (2012), Paris (2013), EUROSOI 2014 will be held in Tarragona, Catalonia, Spain, and will include a short course program, oral and poster sessions, outstanding key-note presentations, as well as ample rooms for informal discussions. EUROSOI covers recent progress in SOI technologies and will be of interest to materials and device scientists, as well as to process, circuits and applications oriented engineers.

Monday, January 27, 2014

8:30 REGISTRATION
9:05-9:20 SHORT COURSE OPENING
9:20-11:00 PART 1 - EDS MINI-COLLOQUIUM ON SOI TECHNOLOGY 
9:20-10:10 "Process Challenges for Advanced Ge CMOS Technologies" Cor Claeys (IMEC, Leuven, Belgium)
10:10-11.00 "From Floating-Body Memory to Unified Memory on SOI" Sorin Cristoloveanu (INPG, Grenoble, France)
11:00-11:30 COFFEE BREAK
11:30-12:20 "Fabrication Challenges for sub-10 nm Technology nodes" Michael Ostling (KTH, Stockholm, Sweden)
12:20-13:00 "ESD protection of FD and MuG SOI CMOS Chips" Dimitris Ioannou (George Mason University, Fairfax, VA, USA)
13:00-14:30 LUNCH
14:30-15:50 Part 2 -EUROSOI TUTORIAL 
14:30-15:20 "Advanced SOI MOSFET architectures" Jason Woo (UCLA, CA, USA)
15:20-16:00 "SOI CMOS sensors, transistors and circuits for ultra-low-power and harsh environment applications" Denis Flandre (UCL, Louvain-la-Neuve, Belgium)
16:00-16:30 COFFEE BREAK
16:30-18:00 SOI MOSFET CHARACTERIZATION 
16:30-17:20 "On the threshold voltage and interface coupling in advanced SOI MOSFETs" Tamara Rudenko (ISP, Kyiv, Ukraine)
17:20-18:00 "From SOI MOSFET to Spin MOSFET: a modeling approach" Viktor Sverdlov (Tu-Wien, Austria)
20:30 EUROSOI RECEPTION

Tuesday January 28, 2014 

8:15 REGISTRATION
8:45-9:00 OPENING
9:00-11:00 PLENARY SESSIONS 
9:00-9:40 "Taking the next step on advanced HKMG SOI technologies -from 32 nm PD SOIvolume production to 20/28 FD SOI and beyond" Manfred Horstmann (Globalfoundries, Dresden, Germany) invited talk
9:40-10:20 INVITED TALK 
Heike Riel (IBM Research, Zurich) -invited talk
10:20-11:00 "Beyond Si CMOS: Benefits and Challenges " Rafael Rios (Intel, Portland OR, USA) -invited talk
11:00-11:20 COFFEE BREAK
11:20-13:00 SOI MATERIALS TECHNOLOGY AND CHARACTERIZATION 
11:20-11:40 Process and performance of Copper TSVs Lado Filipovic et al.
11:40-12:00 Increasing mobility and spin lifetime with shear strain in thin silicon films Dmitri Osintsev et al.
12:00-12:20 A Comparative Study of Variability of RTN Power Spectral Densities in Bulk and SOIMOSFETs  Louis Gerrer et al.
12:20-12:40 Low temperature noise spectroscopy of p-channel SOI FinFETs Bogdan Cretu et al.
12:40-13:00 Channel Length Influence on the Low-Frequency Noise of Strained 45o Rotated Triple Gate SOI nFinFETs Marcio Alves Sodre de Souza et al.
13:20-14:10 LUNCH
14:10-15:50 SOI MOSFET TECHNOLOGY 
14:10-14:30 Impact of S/D doping profile into electrical properties in nanoscaled UTB2SOI  devices Carlos Sampdero et al.
14:30-14:50 TCAD investigation on a formal Neuron device in 28nm UTBB FDSOI technology Philippe Galy et al.
14:50-15-10 Dual ground plane for high-voltage MOSFET in UTBB FDSOI Technology Antoine Litty et al.
15:10-15:30 Trigate NanoWire MOSFETs Analog Figures of Merit Kilchytska, Valeriya et al.
15:30-15:50 Electrostatically-doped SL FET optimized to meet all the ITRS power targetsat V_DD=0.4 V Elena Gnani et al.
15:50-16:00 COFFEE BREAK
16:00-17:20 SOI MOSFET CHARACTERIZATION 
16:00-16:20 Enhanced Dynamic Threshold Voltage UTBB SOI nMOSFETs Katia Sasaki et al.
16:20-16:40 Parasitic bipolar effect in advanced FD SOI MOSFETs: experimental evidence andgain extraction Fanyu Liu et al.
16:40-17:00 Impact of Lateral Fin-Width Non-Uniformity of FinFETs Clarissa Prawoto et al.
17:00-17:20 Surface effects on split C-V measurements on SOI wafers Luca Pirro et al.
17:20-17:40 Impact of Self-Heating on UTB MOSFET ParametersS ergej Makovejev at al.
17:40-18:00 POSTER BRIEFING (3 MIN EACH) 
18:00-19:40 POSTER SESSION 
Subthreshold Behavior of the PD SOI NMOS Device Considering BJT and DIBL Effects James Kuo et al.
Investigation of Statistical Effects on Reliability of SOI FinFETs Including Sidewall Crystal Orientation Salvatore Amoroso et al.
Powering the More than Moore Electronics with i-MOSLining Zhang et al.
Analysis of Short-Channel Effect in SOTB-MOSFET for Ultra-Low Power Applications Hidenori Miyamoto et al.
2D Analytical Modeling of the Trap-Assisted-Tunneling Current in Double-GateTunnel-FETs Michael Graef et al.
Improved Compact Current Model for FinFETs Based in a New Geometric Approach Arianne Pereira et al.
Capability of the IDS Analytical Model on Predicting the Diamond Variability by Usingthe F-Test Statistic Evaluation Salvador Gimenez et al.
An appraise of the sources of electrical parameters variation in DGMOS Rodrigo Picos et al.
An analytical model for the inversion charge distribution in GAA MOSFETs with rounded corners Francisco Ruiz et al.
The Negative World-line Holding Bias Effect on the Retention Time in FBRAMs Sara Santos et al.
20:30 GALA DINNER

Wednesday January 29, 2014 

8:30-10:30 SOI MOSFET MODELLING 
8:30-8:50 Comprehensive Low-Field Mobility Modeling in Nano-Scaled SOI Channels Zlatan Stanojevic et al.
8:50-9:10 A comprehensive DC current model to describe FinFET self-heating effects Benito Gonz‡lez et al.
9:10-9:30 Channel-Length Impact on Supercoupling Effect in FD-MOSFETs Carlos Navarro et al.
9:30-9:50 Substrate Effect on Threshold Voltage of long and short channel UTBB SOI nMOSFETs Joao Martino et al.
9:50-10:10 In depth characterization of electron transport in 14nm FD-SOI nMOS devices Minju Shin et al.
10:10-10:30 Role of the gate in ballistic nanowire SOI MOSFET Anurag Mangla et al.
10:30-10:50 COFFEE BREAK
10:50-13:10 CIRCUITS, MEMORIES AND SENSORS 
10:50-11:30 "Future of Multi-gate CMOS Technology" Hiroshi Iwai (University of Tokyo, Japan)
11:30-11:50 Impact of SEU on Bulk and FDSOI CMOS SRAM Walter Enrique Calienes Bartra et al.
11:50-12:10 Mechanical Characterization and Modelling of Lorentz Force Based MEMS Magnetic Field Sensors Petros Gkotsis et al.
12:10-12:30 Performance of Source-Follower Buffers Implemented with Junctionless Nanowire nMOS Transistors Michelly Souza et al.
12:30-12.50 PMOSFET-based Pressure Sensors in FD SOI Technology Benoit Olbrechts et al.
12:50-13:10 Performance of Common-Source current mirrors with asymmetric self-cascode SOInMOSFETs  Rafael Assalti et al.
13:10-14:20 LUNCH
14:20-16:10 BEYOND CMOS: NANOWIRES AND JUNCTIONLESS TRANSISTORS 
14:20-15:00 "2D semiconductor channels for ultimate thickness scaling and other versatile applications" Athanasios Dimoulas (IMS, Demokritos, Athens, Greece)
15:00-15:20 A way to solve Poisson equation en cylindrical coordinates to obtain a compact model for Junctionless Gate All Around MOSFET Franois Lime et al.
15:20-15:40 Explicit analytical charge and capacitance models for Junctionless Surrounding GateTransistors  Oana Moldovan et al.
15:40-16:00 Performance Evaluation of Stacked Gate-All-Around MOSFETs Meng-Hsueh Chiang et al.
16:00-16:20 Modeling of Quantization Effects in Nanoscale DG Junctionless MOSFETs Thomas Holtij et al.
16:20-16:30 COFFEE BREAK
16:30-16:50 BEYOND CMOS (TFETs) 
16:30-16:50 Heterojunction TFET inverters providing better performance than multi-gate CMOS at sub 0.3V Vdd Elena Gnani et al.
16:50-17:10 Transport mechanism influence on Vertical Nanowire-TFET analog performance as a function of temperature Paula Agopian et al.
17:10-17:30 3D Modeling of Direct Band-to-Band Tunneling in Nanowire TFETs. Lidija Filipovic et al.
17:30-17:50 Influence of the gate oxide thickness on the Analog Performance of vertical Nanowire-Tunnel FETs with Ge Source Felipe Neves et al.
17:50-18:10 Influence of a precisely positioned channel dopant on the performance of gate-allaround Si nanowire transistor: a full 3D NEGF simulation study Vihar Georgiev et al.
18:10-18:20 CONCLUSIONS AND ANNOUNCEMENTS 

[Final Program] 11th International Workshop on Compact Modeling

11th International Workshop on Compact Modeling (IWCM 14)

January 23 (Thursday), 2014

Suntec Singapore Convention and Exhibition Centre (Room 309)

Workshop Program

9:00-9:10am Welcome address
Mansun Chan (workshop chair)

Session I: Modeling for Compact Semiconductor
Session Chair: Lining Zhang

9:10-9:35am Challenges and Prospects of Compact Modeling for Future Generation III-V/Si Co-integrated ULSI Circuit Design
Xing Zhou, Siau Ben Chiah, Binit Syamal, Hongtao Zhou, Arjun Ajaykumar, and Xu Liu; Nanyang Technological University, Singapore
9:35-10:00am A Large Signal Model for InP/InGaAs Double Heterojunction Bipolar Transistors
Yan Wang and Yuxia Shi; Tsinghua University, China
10:00-10:25am Analytical Modeling for AlGaN/GaN HEMTs
Aixi Zhang, Lining Zhang, Zhikai Tang, Xiaoxu Cheng*, Yan Wang*, Kevin J. Chen, and Mansun Chan; The Hong Kong University of Science and Technology, Hong Kong, China; *Tsinghua University, China

10:25-10:40am Break

Session II: Non-Classical Device Modeling and Platform
Session Chair: Xing Zhou

10:40-11:05am Developing i-MOS as a Compact Model Standardization Platform
Lining Zhang and Mansun Chan; The Hong Kong University of Science and Technology, Hong Kong, China
11:05-11:30am An Analytic Model for Nanowire Tunnel-FETs
Ying Liu, Jin He, Mansun Chan*, Caixia Du**, Yun Ye, Wei Zhao, Wen Wu and Wenping Wang; Peking University Shenzhen SOC Key Laboratory, China; *The Hong Kong University of Science and Technology, Hong Kong, China; **Shenzhen Huayue Teracale Chip Electronic Limited Co., China
11:30-11:55am A Channel Potential Based Model for SiO2- Core Si-Shell SRGMOSFET
Xiangyu Zhang, Jin He, Mansun Chan*, Caixia Du**, Yun Ye, Wei Zhao, Wen Wu and Wenping Wang; Peking University Shenzhen SOC Key Laboratory, China; *The Hong Kong University of Science and Technology, Hong Kong, China; **Shenzhen Huayue Teracale Chip Electronic Limited Co., China

11:55am-2:00pm Lunch

Session III: Power Device Modeling
Session Chair: Young June Park

2:00-2:25pm Compact Modeling of the Reverse Recovery Effect in LDMOS Body Diode (Invited)
M. Miyake; Hiroshima University, Japan
2:25-2:50pm Compact Modeling of the SiC IGBT Including the Switching at High Temperature
K. Matsuura, M. Miura-Mattausch, M. Miyake and H. J. Mattausch; Hiroshima University, Japan
2:50-3:15pm Experimental Verification of Power MOSFET Model under Switching Operations
A. Saito, M. Miura-Mattausch, M. Miyake, T. Umeda and H.J. Mattausch; Hiroshima University, Japan

3:15-3:30pm Break

Session IV: Reliability Modeling
Session Chair: Jin He

3:30-3:55pm 3D Monte Carlo Reaction-Diffusion Simulation Framework to model Time Dependent Dielectric Breakdown in BEOL Oxide
Seong Wook Choi and Young June Park; Seoul National University, Korea
3:55-4:20pm Development of NBTI and Channel Hot Carrier (CHC) Effect Models and their Application for Circuit Aging Simulation
Chenyue Ma, Hans Jürgen Mattausch, Kazuya Matsuzawa*, Seiichiro Yamaguchi*, Teruhiko Hoshida*, Masahiro Imade*, Risho Koh*, Takahiko Arakawa* and Mitiko Miura-Mattausch; Hiroshima University, Japan; * Semiconductor Technology Academic Research Center, Japan
4:20-4:45pm Modeling of the Surface Charges on Au Electrode Including Pseudocapacitance
Jooseong Kwon, Intae Jeong, Sungwook Choi and Young June Park; Seoul
National University, Korea

4:45-4:55pm Closing Remarks
Hans Juergen Mattausch (workshop co-chair)

Thanks to  Adele HARS, we can share this post:

The FD-SOI Papers at IEDM ’13

Posted by Adele HARS on December 16, 2013
Tagged with 10nm, 14nm, 28nm, conference, design, FD-SOI, GlobalFoundries, Hitachi, IBM, Leti, manufacturing, R&D, Renesas, silicon-on-insulator, Soitec, ST, strain, Synopsys, U.Tokyo, UTBB FD-SOI was a hot topic at this year’s IEEE International Electron Devices Meeting (IEDM) (www.ieee-iedm.org), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.
The FD-SOI papers featured high performance, low leakage, ultra-low power (0.4V),  excellent variability, reliability and scalability down to the 10 nm node using thin SOI and thin BOX substrate. Performance boosters using high mobility materials such as thin strain Si, Ge, and III-V on-Insulator were also presented.
Brief summaries of the FD-SOI papers, culled from the Advance Program (and some of the actual papers) follow.
9.2 High Performance UTBB FDSOI Devices Featuring 20nm Gate Length for 14nm Node and Beyond (STMicroelectronics, Leti, IBM, Renesas, Soitec, GlobalFoundries)

This was the big paper reporting on ST’s flavor of high-performance FD-SOI (UTBB, which stands for ultra-thin-body-and-box) with 20nm gatelength, which target the 14nm node. In addition to excellent results, the paper demonstrated that  “…FD-SOI reliability is superior to Bulk devices.”

[8] C. Auth, et al, VLSI, p.131, 2012 [9] C.-H. Jan, et al, IEDM, p.44, 2012

Specifically, the alliance reports, for the first time, on high performance UTBB FD-SOI devices with a gate length (LG) of 20nm and BOX thickness (TBOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET). Competitive effective current (Ieff) reaches 630μA/μm and 670μA/μm for NFET and PFET, respectively, at off current (Ioff) of 100nA/μm and Vdd of 0.9V.

Excellent electrostatics are obtained, demonstrating the scalability of these devices to14nm and beyond. Very low AVt (1.3mV•μm) of channel SiGe (cSiGe) PFET devices is reported for the first time. BTI was improved >20% vs a comparable bulk device. The paper concludes with evidence of continued scalability to 10nm 

and below.

“The effective current (Ieff), as a function of Ioff, is shown in Fig. 4. At Vdd=0.9V, NFET/PFET Ieff reach 630/670μA/μm at Ioff=100nA/μm, respectively. They are the best performing FDSOI CMOS devices reported so far, featuring non-strained Si channel NFET and strained SiGe channel PFET.”

7.3 Innovative ESD protections for UTBB FD-SOI Technology (STMicroelectronics, IMEP-LAHC)

ESD (electrostatic discharge) protection is often cited as a challenge in FD-SOI, and the ESD devices are typically put into a “hybrid” section of the chip, where the top silicon and insulator are etched away exposing the “bulk” silicon base wafer. In this paper, however, the ST-IMEP team presented FD-SOI ESD protection devices that achieve “remarkable performance in terms of leakage current and triggering control.” They demonstrate “ultra-low leakage current below 0.1 pA/μm and adjustable triggering (1.1V < Vt1 < 2.6V) capability. These devices rely on gate-controlled injection barriers and match the 28nm UTBB-FDSOI ESD design window by triggering before the nominal breakdown voltage of digital core MOS transistors.”

7.4 Comparison of Self-Heating Effect (SHE) in Short-Channel Bulk and Ultra-Thin BOX SOI MOSFETs: Impacts of Doped Well, Ambient Temperature, and SOI/BOX Thicknesses on SHE (Keio University, AIST)

This paper refutes those who say that the self-heating effect (SHE) is a bigger concern for SOI-based devices than bulk. The researchers investigated and compared bulk and SOI FETs including 6-nm ultra-thin (UT) BOX devices. They clarified, for the first time, that SHE is not negligible in bulk FETs, mainly due  to a decrease in the thermal conductivity of the more heavily doped well.  They found that the channel temperature of 6-nm UT BOX SOI FETs is close to that of bulk FETs at a chip temperature under operations. They then proposed a thermal-aware FD-SOI device design structure based on evaluated BOX/SOI thickness dependences of SHE. They concluded that SHEs in UTBB FETs with raised S/D and/or contact pitch scaling could be comparable to bulk FETs in deeply scaled nodes.

20.3 Gate-Last Integration on Planar FDSOI MOSFET: Impact of Mechanical Boosters and Channel Orientations  (Leti, ST)

This paper presents the industry’s first “gate last” (GL) results for FD-SOI, with ultra-thin silicon body (3-5nm) and BOX (25nm).  The team successfully fabricated transistors down to the 15nm gate length, with metal-last on high-k first (TiN/HfSiON). They thoroughly characterized the gate stack (reliability, work-function tuning on Equivalent Oxide Thickness EOT=0.85nm) and transport (hole mobility, Raccess) for different surface and channel orientations. They report excellent Ion, p=1020μA/μm at Ioff, p=100nA/μm at Vdd=0.9V supply voltage for <110> pMOS channel on (001) surface with in-situ boron doped SiGe Raised Source and Drain (RSD) and compressive CESL. They cite the high efficiency of the strain transfer into the ultra-thin channel (-1.5%), as evidenced by physical strain measurements by dark field holography.

12.4 UTSOI2: A Complete Physical Compact Model for UTBB and Independent Double Gate MOSFETs (ST, Leti)

Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers run before actual manufacturing. In this paper, ST and Leti researchers presented a complete physical compact model called UTSOI2, which is dedicated to Ultra-Thin Body and Box FD-SOI technology, and is able to describe accurately independent double gate operation for sub-20nm nodes. It meets standard Quality and Robustness tests for circuit design applications.

12.5 Mobility in High-K Metal Gate UTBB-FDSOI Devices: From NEGF to TCAD Perspectives (Invited) (ST, Leti, U. Udine, Synopsys, Laboratoire Hubert Curien & Institut d’Optique, IBM)

This paper reviews important theoretical and experimental aspects of both electrostatics and channel mobility in High-K Metal Gate UTBB-FDSOI MOSFETs. With an eye toward optimization, the team presents a simulation chain, including advanced quantum solvers, and semi-empirical Technology Computer Assisted Design (TCAD) tools.

33.2 Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by Balanced P/N Drivability Control with Back-Bias for Ultralow-Voltage (0.4 V) Operation (LEAP, U. Tokyo)

SOTB is what Hitachi calls its flavor of FD-SOI.  The researchers point out that small-variability transistors like SOTB are effective for reducing the operation voltage (Vdd). This paper proposes the balanced n/p drivability for reducing the die-to-die delay variation by back bias for various circuits. Excellent delay variability reduction by this n/p balanced control is demonstrated at ultra-low Vdd of 0.4 V.

2.8: Co-Integration of InGaAs n- and SiGe p-MOSFETs into Digital CMOS Circuits Using Hybrid Dual-Channel ETXOI Substrate (IBM)

ETSOI is IBM’s flavor of FD-SOI, and this paper is about FD-SOI devices using high mobility material for boosting performance. The presenters “demonstrate for the first time on the same wafer and on the same device level a dense co-integration of co-planar nano-scaled SiGe p-FETs and InGaAs n-FETs UTBB FETs. This result is based on hybrid substrates containing extremely-thin SiGe and InGaAs layers on insulators (ETXOI) using double bonding.” They showed a) that it could be done; b) it’s viable hybrid high-mobility dual-channel CMOS; c) it still supports back-biasing for Vt tuning.

5.2 Surface Roughness Limited Mobility Modeling in Ultra-Thin SOI and Quantum Well III-V MOSFETs  (DIEGM – U. Udine)

As with the IBM paper (2.8) above, this paper is about FD-SOI devices using high mobility material for boosting performance. The abstract explains, “This paper presents a new model for surface roughness mobility accounting for the wave-function oxide penetration and can naturally deal with Hetero-Structure. Calibration with experiments in Si MOSFETs results in a r.m.s. value of the SR spectrum in close agreement with AFM and TEM measurements.” The simulated μSR in III-V UTB MOSFETs shows a weaker degradation at small channel thickness (T_w) than predicted by the T_6w law observed in UTB Si MOSFETs.

Please stay tuned for a subsequent ASN post that will cover the meeting’s SOI-FinFET, RF-SOI and advanced device papers.  (The papers themselves are typically available through the IEEE Xplore Digital Libary within a few months of the conference.)

An Update on the OpenPDK for IC Design (by Daniel Payne)

IC designers use EDA tools to implement their logical and physical design, and these tools require foundry-specific information for:

• Design Rule Checking (DRC)
• Layout Versus Schematic (LVS)
• Library Symbols
• Parasitic EXtraction (PEX)

This foundry information is called a Process Design Kit or PDK for short. Now put yourself in the place of the foundry or IDM, and you want to support EDA tools from multiple vendors like: Cadence Design Systems, Mentor Graphics, Synopsys, Silvaco and Tanner EDA. That adds up to a lot of QA and PDK development effort to support so many EDA vendors and tools. There has to be an easier way to create PDKs instead of one vendor at a time.




Read more at the original source