A Cambridge post-graduate student, Marian Rejewski rebuilds Polish Enigma-code-breaking box that paved the way for Turing ... and Victory! https://t.co/hPLDTC9Ocv #paper https://t.co/ZNrvrJN0Zd

A Cambridge post-graduate student, Marian Rejewski rebuilds Polish Enigma-code-breaking box that paved the way for Turing ... and Victory! https://t.co/hPLDTC9Ocv#paper pic.twitter.com/ZNrvrJN0Zd

— Wladek Grabinski (@wladek60) July 15, 2020

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[paper] compact nanowire JAM-MOSFET model

Kamalaksha Baral, Prince Kr Singh, Sanjay Kumar, Manas Ranjan Tripathy,

Ashish Kr Singh, Sweta Chander and S JitA

2-D compact DC model for engineered nanowire JAM-MOSFETs 

valid for all operating regimes

Semiconductor Science and Technology, Vol. 35, No. 8

Abstract: This manuscript reports a 2-D compact analytical model for DC characteristics under all possible regimes of operations of a cylindrical gate (CG) nanowire junctionless accumulation mode (JAM) MOSFET including the effects of various device engineering techniques. Superposition technique with appropriate boundary conditions has been used to solve 2-D Poisson’s equation considering both free/accumulation and depletion charges. The minimum potential concept has been used to conceive the threshold voltage formulation considering the effects of structural and electrical quantum confinements. An optimized device model has been formulated incorporating various device engineering. The potential model could also be used for potential modeling of doped inversion mode MOSFETs. Complete drain current including gate induced drain leakage (GIDL) has been derived from the potential model. Drain current has been derived individually for different regions. Further the effects of temperature and trapped interface charges have been included in the model. A 3-D commercial TCAD has been used to validate the model results of our proposed device. 

Fig: A 2-D cross-sectional view of cylindrical gate nanowire
junctionless accumulation mode MOSFET 

IEEE Events Reveal #Future #Memory And #Storage https://t.co/lfOq1d8BG3 #paper https://t.co/q7p7pc4ZPd

IEEE Events Reveal #Future #Memory And #Storage https://t.co/lfOq1d8BG3#paper pic.twitter.com/q7p7pc4ZPd

— Wladek Grabinski (@wladek60) July 6, 2020

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July 06, 2020 at 11:55AM
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With #128 #Core #Chip, Ampere Seeks to Deliver Reliable Advances [@EETimes] https://t.co/zq3ovp6WPN #paper https://t.co/CLY45rUvGP

With #128 #Core #Chip, Ampere Seeks to Deliver Reliable Advances [@EETimes] https://t.co/zq3ovp6WPN#paper pic.twitter.com/CLY45rUvGP

— Wladek Grabinski (@wladek60) July 6, 2020

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July 06, 2020 at 11:45AM
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@ETH integrates #photonics and #electronics on one #chip https://t.co/Lg1KYDF0RS #paper https://t.co/5HKJTzOR51

@ETH integrates #photonics and #electronics on one #chip https://t.co/Lg1KYDF0RS#paper pic.twitter.com/5HKJTzOR51

— Wladek Grabinski (@wladek60) July 6, 2020

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July 06, 2020 at 11:42AM
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A Vibrant #Semiconductor #Manufacturing #Model for the #US [Semiwiki] https://t.co/rjT2bSloqX https://t.co/WozbLN0s6h

A Vibrant #Semiconductor #Manufacturing #Model for the #US [Semiwiki] https://t.co/rjT2bSloqX pic.twitter.com/WozbLN0s6h

— Wladek Grabinski (@wladek60) July 6, 2020

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$1#billion market for #SiC and #GaN https://t.co/D0ukYu8BAK #paper https://t.co/BVZjWuNXlr

$1#billion market for #SiC and #GaN https://t.co/D0ukYu8BAK #paper pic.twitter.com/BVZjWuNXlr

— Wladek Grabinski (@wladek60) July 2, 2020

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Understand #MOSFET Switch Behavior Via An #LED Driver #Simulation https://t.co/sQ4KYaQpX2 #paper https://t.co/Z2x0VHLVTG

Understand #MOSFET Switch Behavior Via An #LED Driver #Simulation https://t.co/sQ4KYaQpX2#paper pic.twitter.com/Z2x0VHLVTG

— Wladek Grabinski (@wladek60) July 1, 2020

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IEEE SSCS-EDS Distinguished Talks (Webinar) Systematic Design of Analog CMOS Circuits Dr. Paul Jespers, UCLouvain, Louvain-la-Neuve, Belgium July 09th, 13h30 (Brasilia Time, GMT-3) https://t.co/d3HL96l2xT https://t.co/FQOFMq4FJG #paper https://t.co/zelqSxMxGI

IEEE SSCS-EDS Distinguished Talks (Webinar)
Systematic Design of Analog CMOS Circuits
Dr. Paul Jespers, UCLouvain, Louvain-la-Neuve, Belgium
July 09th, 13h30 (Brasilia Time, GMT-3)https://t.co/d3HL96l2xT https://t.co/FQOFMq4FJG#paper pic.twitter.com/zelqSxMxGI

— Wladek Grabinski (@wladek60) June 29, 2020

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Creating A Custom ASIC With The First Open Source PDK: The FOSSi foundation now reports on a new, open PDK project launched by Google and SkyWater Technology https://t.co/6G78tYz4c1 #model https://t.co/NOCZS6YMr5

Creating A Custom ASIC With The First Open Source PDK: The FOSSi foundation now reports on a new, open PDK project launched by Google and SkyWater Technology https://t.co/6G78tYz4c1#model pic.twitter.com/NOCZS6YMr5

— Wladek Grabinski (@wladek60) June 26, 2020

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EEE SSCS-EDS Distinguished Talks (Webinar) Low-power Circuits for IoT Dr. Jorge Fernandes, INESC-ID, Lisbon, Portugal. Next Thursday, June 25th, 2:00 PM (Brasilia Time, GMT-3) https://t.co/wJuF6ryZHW #paper https://t.co/6jrZWrKTAh

EEE SSCS-EDS Distinguished Talks (Webinar)
Low-power Circuits for IoT
Dr. Jorge Fernandes, INESC-ID, Lisbon, Portugal.
Next Thursday, June 25th, 2:00 PM (Brasilia Time, GMT-3) https://t.co/wJuF6ryZHW#paper pic.twitter.com/6jrZWrKTAh

— Wladek Grabinski (@wladek60) June 24, 2020

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Stay up to date with the latest developments in the MEMS areas with IEEE RightNow. Access for J-MEMS. Enjoy temporary Open Access to selected featured publications https://t.co/mxoRhbT802 #paper https://t.co/9h5EV2mEBf

Stay up to date with the latest developments in the MEMS areas with IEEE RightNow. Access for J-MEMS. Enjoy temporary Open Access to selected featured publicationshttps://t.co/mxoRhbT802#paper pic.twitter.com/9h5EV2mEBf

— Wladek Grabinski (@wladek60) June 23, 2020

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[paper] “Extrinsic” Compact Model of the MOSFET Drain Current

V. O. Turin, R. S. Shkarlat, G. I. Zebrev, B. Iñiguez and M. S. Shur

The “Extrinsic” Compact Model of the MOSFET Drain Current Based on a New Interpolation Expression for the Transition Between Linear and Saturation Regimes with a Monotonic Decrease of the Differential Conductance to a Nonzero Value

2020 4th IEEE EDTM, Penang, Malaysia

2020, pp. 1-4

doi: 10.1109/EDTM47692.2020.9117810

Abstract: Previously, we proposed a new interpolation expression to bridge the transition between the linear and the saturation regimes of “intrinsic” MOSFET. This approach, in contrast to the traditional one, gives a monotonic decrease of the differential conductance from the maximum value in the linear regime to the minimum value in the saturation regime. Later, we proposed a linear approximation for an “extrinsic” MOSFET drain current dependence on the “extrinsic” drain bias in the saturation regime for not very high drain bias when nonlinear effects can be neglected. To obtain this approximation, an equation for the output differential resistance of the “extrinsic” MOSFET in saturation regime was obtained, that is similar to the result known from the theory of the common source MOSFET amplifier with source degeneration. In this paper, we combine these two results and present an “extrinsic” compact model for a short-channel MOSFET above threshold drain current with proper account of the differential conductance in the saturation regime.

#SilTerra - #MEMS Technology Roadmap https://t.co/X0g0M0ImoL #paper https://t.co/n0Nthns32a

#SilTerra - #MEMS Technology Roadmap https://t.co/X0g0M0ImoL #paper pic.twitter.com/n0Nthns32a

— Wladek Grabinski (@wladek60) June 19, 2020

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[Short Course] Modeling and Simulation of Nano-Transistors

Short Course

Modeling and Simulation of Nano-Transistors

6 - 10 July 2020 at Outreach Auditorium,IIT Kanpur

http://www.iitk.ac.in/nanolab/sc2020/

by Prof. Yogesh S. Chauhan

Nanolab, IIT Kanpur

http://home.iitk.ac.in/~chauhan/

Aim: VLSI design will soon use transistors whose size will be as small as 10nm. The aim of this short course is to educate and train bright minds on different aspects of Nano-transistors. Modeling especially compact modeling is the heart of circuit simulation. TCAD simulations are used for early device design and to understand the internal physics of transistor. Electrical characterization includes current and capacitance voltage measurement of transistor. RF measurement is an exciting area which involves understanding of devices as well as high frequency effects. This short course will cover various topics in modeling, simulation and characterization of transistors especially at nanoscale.

Topics: (1) VLSI design and Nanoelectronics, (2) Physics and Operation of MOSFET, (3) SPICE and Circuit simulation, (4) TCAD simulation: Theory and demonstration, (5) Compact Modeling: Theory and demonstration, (6) Scaling and Moore's Law, (7) Nano-Transistors: FinFET, FDSOI, Negative Capacitance FET, Nanosheet FETs, 2D-FETs etc. (8) Characterization: Current and capacitance measurement, (9) RF CMOS and GaN High Electron Mobility Transistors

Hands-on Sessions: (1) Verilog-A coding, (2) SPICE ckt. Simulation, (3) TCAD Simulation, (4) Parameter Extraction

Coordinator: Prof. Yogesh S. Chauhan Dept. of Electrical Engg., IIT Kanpur

Registration: This short course has been postponed to end of this year or early next year due to ongoing pandemic. New Dates will be announced once normalcy returns in the country.

A Benchmark Study Of Complementary-Field Effect Transistor (#FET) Process Integration Options: Comparing #Bulk vs. #SOI vs. DSOI Starting Substrates https://t.co/rYE24rym7L #paper https://t.co/T3ECdVJa5c

A Benchmark Study Of Complementary-Field Effect Transistor (#FET) Process Integration Options: Comparing #Bulk vs. #SOI vs. DSOI Starting Substrates https://t.co/rYE24rym7L #paper pic.twitter.com/T3ECdVJa5c

— Wladek Grabinski (@wladek60) June 17, 2020

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[paper] Compact Model for Ferroelectric FET

Lu, Darsen, Sourav De, Mohammad Aftab Baig, Bo-Han Qiu, and Yao-Jen Lee

Computationally efficient compact model for ferroelectric field-effect transistors 

to simulate the online training of neural networks

Semiconductor Science and Technology (2020)

DOI: 10.1088/1361-6641/ab9bed

Abstract: In this paper, a compact drain current formulation that is simple and adequately computationally efficient for the simulation of neural network online training was developed for the ferroelectric memory transistor. Tri-gate ferroelectric field effect transistors (FETs) with Hf0.5Zr0.5O2 gate insulators were fabricated with a gate-first high-k metal gate CMOS process. Ferroelectric switching was confirmed with double sweep and pulse programming and erasure measurements. Novel characterization scheme for drain current was proposed with minimal alteration of ferroelectric state in subthreshold for accurate threshold voltage measurements. The resultant threshold voltage exhibited highly linear and symmetric across multilevel states. The proposed compact formulation accurately captured the FET gate-bias dependence by considering the effects of series resistance, Coulomb scattering, and vertical field dependent mobility degradation.

Fig.: Transmission electron micrograph of the fabricated tri-gate Fe

finFET device across the fin, with approximately 60 nm fin width, 30 nm fin

height, and 10 nm HZO Fe layer.

Acknowledgements: This work was jointly supported by the Ministry of Science and Technology (Taiwan) grant MOST–108–2634–F–006–08 and is part of research work by MOST’s AI Biomedical Research Center. We are grateful to the Taiwan Semiconductor Research Institute for nanofabrication facilities and services and to Dr. Wen-Jay Lee and Nan-Yow Chen of the National Center for High-Performance Computing for helpful suggestions on AI computation. This manuscript was edited by Wallace Academic Editing.

#Samsung #MOSIS Collaboration https://t.co/IOrXK5W1Y8 #paper https://t.co/VXZqf03bmY

#Samsung #MOSIS Collaboration https://t.co/IOrXK5W1Y8 #paper pic.twitter.com/VXZqf03bmY

— Wladek Grabinski (@wladek60) June 17, 2020

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June 17, 2020 at 09:14AM
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Learning with brain chemistry https://t.co/UJRbFdHuUh #paper https://t.co/PB4Ty0moUg

Learning with brain chemistry https://t.co/UJRbFdHuUh #paper pic.twitter.com/PB4Ty0moUg

— Wladek Grabinski (@wladek60) June 16, 2020

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[paper] TFT Compact Modeling

Arun Dev Dhar Dwivedi, Sushil Kumar Jain, Rajeev Dhar Dwivedi and Shubham Dadhich

Numerical Simulation and Compact Modeling 

of Thin Film Transistors for Future Flexible Electronics

Submitted: July 4th 2019Reviewed: October 28th 2019Published: June 10th 2020

DOI: 10.5772/intechopen.90301

Abstract: In this chapter, we present a finite element method (FEM)-based numerical device simulation of low-voltage DNTT-based organic thin film transistor (OTFT) by considering field-dependent mobility model and double-peak Gaussian density of states model. Device simulation model is able to reproduce output characteristics in linear and saturation region and transfer characteristics below and above threshold region. We also demonstrate an approach for compact modeling and compact model parameter extraction of organic thin film transistors (OTFTs) using universal organic TFT (UOTFT) model by comparing the compact modeling results with the experimental results. Results obtained from technology computer-aided design (TCAD) simulation and compact modeling are compared and contrasted with experimental results. Further we present simulations of voltage transfer characteristic (VTC) plot of polymer P-channel thin film transistor (PTFT)-based inverter to assess the compact model against simple logic circuit simulation using SmartSpice and Gateway.

Fig.: Schematic cross-sectional diagram of organic TFTs 

along with the chemical structure of SAM and organic semiconductor.

Acknowledgments: The authors are thankful to SERB, DST, Government of India, for the financial support under Early Career Research Award (ECRA) for Project No. ECR/2017/000179.