[mos-ak] [Final Program] MOS-AK LatAm Webinar, Dec. 12, 2025

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

MOS-AK LatAm Workshop

(online), Dec. 12, 2025

The End‑of‑Year MOS-AK Workshop/Webinar on Compact/SPICE Modeling will be held online on Dec. 12, 2025. We invite you to join this webinar to learn from the experts in Compact SPICE modeling, Verilog‑A standardization, and FOSS CAD/EDA IC design support for OpenPDKs, internationally, with particular focus on Latin America

Venue: MOS-AK LatAm (Webinar)
Online Webinar Access Link: https://meet.jit.si/MOS-AK_LA_2025

• Final Workshop Program: Dec. 12 2025
San Francisco, 09:00 - 11:00
Rio de Janeiro, 14:00 - 16:00
Geneve, 18:00 - 20:00

T_1	OpenPDK LatAm Krzysztof Herman IHP (D)
T_2	AI/ML-Driven Device Modeling for Advanced Nodes, RF and Power Applications Fahad Usmani Keysight Technologies (US)
T_3	Design and Integration of Multiple Open-Source Analog Circuits Fabricated in SKY130 Technology within Silicluster v2 Uriel Jaramillo Toral* Hector Emmanuel Muñoz Zapata and Susana Cisneros Ortega CINVESTAV (MX)
T_4	SemiCoLab, A Multi-Project ASIC Platform for Democratizing Chip Design Emilio Baungarten, Susana Ortega, Miguel Rivera, and Francisco Javier CINVESTAV (MX)
T_5	Building an Ecosystem Through IC Education in Colombia: A Model for Emerging Semiconductor Regions Juan Sebastián Moya Baquero SymbioticEDA
T_6	Silicon-Proven Learning With OpenPDKs and MPW Access for IC Education Eduardo Holguin Weber Universidad San Francisco de Quito (EC)
T_7	OpenPDK Mismatch Testchip Juan Pablo Martinez Brito CEITEC S.A. (BR)
T_8	Physics-Based Modeling and Charge Density Saturation in GaN/AlGaN MOS-HEMTs Ashkhen Yesayan, Farzan Jazaeri, Jean-Michel Sallese EPFL (CH)

W.Grabinski for Extended MOS-AK Committee

WG111225

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[paper] Noise Propagation and Statistic Variability in MOSFETs

Raphael Chatzipantelis, Loukas Chevas, Nikolaos Makris and Matthias Bucher

Noise Propagation and Statistic Variability in MOSFETs Using Probability Density Functions

Fluctuation and Noise Letters (Accepted Paper)

DOI: 10.1142/S0219477525400255

1) School of Electrical and Computer Engineering, Technical University of Crete, Chania 73100, Greece
2) Foundation for Research and Technology Hellas, Heraklion 70013, Greece,

Abstract: Probability density functions using stochastic methods are shown to be an effective tool in the context of MOSFET noise and variability modeling. These methods are employed here in the context of the charge-based EKV MOSFET model. As an example, a Gaussian noise density function applied at the gate or the source of a MOSFET causes a corresponding drain current noise density function, which may be expressed analytically as a function of inversion coefficient only. The same expression may be used to model drain current variability due to MOSFET parameters such as threshold voltage. Furthermore, the method is extended to variations of quantities such as transconductance and transconductance-to-current ratio. The method shows promise in variability modeling of MOSFETs and may complement traditional approaches.

FIG: Comparing the traditional ”small-signal” transconductance method with the stochastic PDF method for 𝑖𝑓, derived from the charge-based model, where in both cases the same noise (or variability) at the gate is applied (𝑉𝐺= 87mV, 𝜎𝑉𝐺=10mV), centered at 𝑖𝑓=2, showing slightly different mean and ±3𝜎 values, while the tail distributions differ significantly.

Acknowledgements: The authors gratefully acknowledge Dr. Predrag Habas from EM Microelectronic S.A. for valuable discussions and wafers for noise and statistical analysis. This work was partly funded by the European Union, and by Greek National funds, under the topic DIGITAL- Chips-2024-SG-CCC-1 - Competence Centers, Project No 101217803 - HCCC.

[semiwiki] Revolution EDA

Revolution EDA: A New EDA Mindset for a New Era

by Semiwiki Admin in Category: EDA on 11-17-2025 at 6:00 am

Key Takeaways

• Revolution EDA introduces an open-source core platform inspired by Visual Studio Code, allowing rapid development and integration with modern machine learning workflows.
• The platform uses JSON for design data storage, making it AI-readable and eliminating data format friction, which contrasts with traditional binary databases.
• Revolution EDA provides a complete front-end design environment with advanced schematic and layout editors, incorporating Python for dynamic functionalities.

Murat Eskiyerli, PhD, is the founder of Revolution EDA  with the tagline “A new EDA mindset for a new era.”  The revolution won’t happen overnight. But it has to start somewhere [ read more... ] 

[mos-ak] [Announcement] MOS-AK LatAm Webinar, Dec. 11-12, 2025

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

MOS-AK Workshop

LatAm (online), Dec. 11-12, 2025

The End‑of‑Year MOS-AK Workshop/Webinar on Compact/SPICE Modeling will be held online on December 11–12, 2025. We invite you to join this webinar and learn from experts in Compact SPICE modeling, Verilog‑A standardization, and FOSS CAD/EDA design support for OpenPDKs. The MOS-AK LatAm Workshop provides a forum to: Strengthen networks and discussions among experts in compact/SPICE modeling; Promote open information exchange on Verilog‑A standardization; Connect academic and industrial specialists in the modeling field; Gather feedback from technology manufacturers, circuit designers, and CAD/EDA tool developers supporting foundry/fabless interface strategies with a focus on OpenPDKs (e.g., Skywater/GF CMOS, IHP RF BiCMOS)

 

Important Dates:

• 1st Announcement: Nov. 2025
• Final Workshop Program: Dec.1 2025
• MOS-AK LatAm online/webinar: Dec. 11-12, 2025

MOS-AK/LatAm Speakers Tentative List (alphabetic order):

• Sergio Bampi, Mateus Grellert and team at UFRGS (BR)
• Juan Pablo Martinez Brito, CEITEC S.A. (BR)
• Carlos Galup, Márcio Cherem Schneider and team at UFSC (BR))
• Krzysztof Herman, IHP (D)
• Eduardo Holguín and team at Universidad San Francisco de Quito (EC)
• Uriel Jaramillo and team from CINVESTAV (MX)
• Peter Lee, Si2 CMC Chair (US)
• Jorge Ivan Marin Hurtado, Universidad del Quindío (CO)
• Mehdi Saligane, Uni. Brown (US) IEEE SSCS TC-OSE Chair
• Fahad Usmani, Keysight (US)

Online Abstract Submission will be open (any related enquiries can be sent to abstracts@mos-ak.org)
Online Free Registration will be open (any related enquiries can be sent to registration@mos-ak.org)

W.Grabinski for Extended MOS-AK Committee

WG221125

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[C4P] ICMC2026 Submission Deadline: February 1, 2026 (4-page paper)

ICMC2026 | July 30-31, 2026| Long Beach, CA

Call for Papers
Submission Deadline: February 1, 2026  (4-page paper)

The Compact Model Coalition (CMC) brings academia and industry partners together in the development and standardization of compact models for semiconductor devices. For more than 30 years, the CMC has been instrumental in creating standardized and verified models for designers to use in their increasingly complex circuits for SPICE simulation. The CMC is organizing the second edition of the International Compact Modeling Conference, cosponsored by IEEE EDS. It will focus uniquely on compact device models, their development, and broad application in the semiconductor industry. You are invited to participate in the evolution of these models, guiding model development to help circuit designers achieve the best circuit performance possible, and enabling foundries to leverage the strength of their device fabrication to the full extent. Join world experts in design, process technology, and model development for a two-day in-person event to discuss state-of-the-art semiconductor device modeling, offering a rare opportunity to present and learn about this core element of circuit design and how to get the most from these global collaborations.

 
HIGHLIGHTED THEMES FOR ICMC 2026 

This year, ICMC especially encourages submissions in the following domains: 

• Electrostatic Discharge (ESD) modeling for protection design
• Modeling of parasitic BJT activation, snapback behavior, ESD stress and breakdown, transient response, failure prediction, etc.
• Reliability and aging-aware compact models and simulation techniques
• for degradation mechanisms such as Bias Temperature Instability (BTI), Hot Carrier Degradation (HCI), Time Dependent Dielectric Breakdown (TDDB)
• self-heating and circuit reliability prediction
• AI or Machine Learning for model development, parameter extraction, circuit simulation efficiency, etc. 

GENERAL TOPICS 

 We are also seeking submissions in the following domains.

Application of Device Models Innovative application of CMC standard device models Designer's perspective: best practices, novel use, and benefits of standard device models to improve circuit design and system performance. Use of compact models to demonstrate foundry device capabilities Device Model Development Modeling of physical phenomena: Statistical variation, noise and fluctuations, RF and high-frequency effects, layout effects, etc. Methodologies to assist in model development, practices for coding, quality assurance, circuit simulator integration, etc. Parameter extraction, measurement techniques, model calibration, validation, and verification methodologies.	Model Enhancements and Implementations Model extensions to capture additional device features (leakage, capacitance, second-order dependencies)or expand the operating range of existing devices (bias, power, temperature, frequency, etc.) Model enhancements to support the design of new or demanding circuits Model workflow, implementation, and integration into the design environment (PDK) Computing/simulation platforms, simulation algorithms, and methodologies to improve simulation performance (parallel processing, etc.) Models for established device types that currently lack standardization. Emerging devices Modeling of emerging and future devices:compact models for novel device technologies and architectures that could further revolutionize circuit performance and design flow. For example, complementary FET, ferroelectric devices, silicon photonics, MRAM, RRAM, cryogenic, quantum computing, 2D-materials, oxide semiconductors, etc.
IMPORTANT DATES February 1, 2026 Submission deadline  (4-page paper) April 6, 2026 Acceptance notification May 10, 2026 Final version for publication July 30-31, 2026 Conference takes place For more details, visit: 2026.si2-icmc.org	ICMC2026 COMMITTEE General Chair: Shahed Reza (Sandia National Laboratories) Vice Chair: Harshit Agarwal (IIT Jodhpur) Technical Program Chair: Gert-Jan Smit (NXP) Technical Program Vice-Chair: Girish Pahwa (NYCU Taiwan) Treasurer: Leigh Anne Clevenger (Si2) Publicity Committee Chair: Wladek Grabinski (MOS-AK)