2 Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea
3 Inter-University Semiconductor Research Center, Seoul National University, Seoul 08826, South Korea
4 School of Electrical and Computer Engineering, University of Seoul, Seoul 02504, South Korea
5 School of Advanced Fusion Studies, University of Seoul, Seoul 02504, South Korea
6 School of Electronic and Electrical Engineering, Kyungpook National University, Daegu 41566, South Korea
ABSTRACT: Recently, three-dimensional FLASH memory with multi-level cell characteristics has attracted increasing attention to enhance the capabilities of artificial intelligence (AI) by leveraging computingin-memory (CIM) systems. The focus is to maximize the computing performance and design FLASH memory suitable for various AI algorithms, where the memory must achieve a highly controllable multi-level threshold voltage (VT). Therefore, we developed a SPICE compact model that can rapidly simulate charge trap FLASH cells for CIM to identify optimal programming conditions. SPICE simulation results of the transfer characteristics are in good agreement with the results of experimentally fabricated FLASH memory, showing a low error rate of 10%. The model was also validated against the results obtained from the TCAD tool, showing that a consistent VT change was computed in a shorter time than that required using TCAD. Then, the developed model was used to comprehensively investigate how single or multiple gate voltage (VG) pulses affect VT. Moreover, considering recent FLASH memory fabrication processes, we found that grain boundaries in polycrystalline silicon channel materials can be involved in deteriorating gate controllability. Therefore, optimizing the pulse scheme by correcting potential errors identified in advance through fast SPICE simulation can enable the accurate achievement of the specific analog states of the FLASH cells of the CIM architecture, boosting computing performance.
Acknowledgements: This work was supported in part by the Institute of Information and Communications Technology Planning and Evaluation (IITP) funded by the Korea Government (MSIT) under Grant 2021-0-01764-001; in part by the National Research Foundation of Korea (NRF) funded by the Korean Government (MSIT) under Grant RS-2023-00208661; in part by the Ministry of Trade, Industry & Energy (MOTIE) under Grant 1415187390; in part by the Korea Semiconductor Research Consortium (KSRC) support program for the Development of the Future Semiconductor Device under Grant 00231985; and in part by the 2023 Research Fund of Kookmin University, South Korea. The work of Jiyong Woo was supported by the National Research and Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT under Grant RS-2023-00258227.
