[Thesis] Verilog-A MOSFET Model for Analog IC Design

Verilog-A Based Implementation of a MOSFET Model for Analog Integrated Circuit Design

Master Thesis by Alba Gallego Velázquez

Defended: July 1, 2025

Technical University of Crete, Chania

Tutor: Prof. Matthias Bucher

Abstract: The present thesis sets out the development and implementation of a compact model of a MOSFET, based on the theoretical EKV model, and implemented using the Verilog-A language. The utilization of simulation and compilation environments, such as the open server OpenVAF and Ngspice, is instrumental in facilitating the effective execution of the work. The construction of a model that can perform the function of an nMOS or a pMOS nanometric operating in a saturated state is facilitated by these. In this model, physical dependencies and second-order effects are incorporated, ensuring the attainment of continuous expressions for all inversion regions. The model's behavior is validated against experimental data by means of simulation. This results in an accurate, compact and versatile model, which is suitable for supporting integrated analog circuits designs with a wide range of values for the inversion coefficient.

Fig: Normalized (𝐺𝑚𝑠 ·𝑈𝑡)/ID of the nMOS vs. the inversion coefficient (IC)

[paper] Gate stack engineering of 2D transistors

Yeon Ho Kim, Donghun Lee, Woong Huh, Jaeho Lee, Donghyun Lee, 

Gunuk Wang, Jaehyun Park, Daewon Ha and Chul-Ho Lee*

Gate stack engineering of two-dimensional transistors.

Nat Electron 8, 770–783 (2025)

DOI: 10.1038/s41928-025-01448-5

* Laboratory of Emerging Electronics & optoElectronics, SNU / julianus95@snu.ac.kr

Abstract: Gate stack engineering has helped enable aggressive device scaling in silicon complementary metal–oxide–semiconductor technology. Two-dimensional (2D) materials are a potential replacement for silicon in next-generation electronics. However, creating gate stacks that are capable of effective and reliable channel control with such materials is inherently challenging owing to the lack of compatible dielectrics and fabrication methods. Here we explore the development of gate stack engineering technologies for two-dimensional transistors. We benchmark key performance metrics for two-dimensional metal–oxide–semiconductor gate stacks against current silicon-based technologies, as well as the targets set by the International Roadmap for Devices and Systems. We also highlight recent advances in ferroelectric-embedded gate stacks, which offer additional functionalities and could be of use in the development of high-speed non-volatile memories and logic-in-memory devices, as well as low-power transistors. Finally, we consider the technical challenges that need to be addressed to develop advanced electronic technologies based on two-dimensional transistors.

FIG: CMOS logic technology roadmap and potential of angstrom-scale 2D transistors

Acknowledgment: This research was supported by the Ministry of Science and ICT under the Next-Generation Intelligent Semiconductor Technology Development Project and the Nano and Material Technology Development Program (Future Technology Labs). The graduate researchers received additional support from BK21 Four and the SNU Graduate School of AI Semiconductor.

[Online Publications] 22nd MOS-AK/ESSERC Workshop in Munich (D) on Sept. 8 2025

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

MOS-AK/ESSERC Workshop

Munich, Sept.8, 2025

The consecutive, 22nd MOS-AK Workshop has been organized as an integral part of 51st ESSERC in Munich (D) on Sept. 8 2025. The MOS-AK workshop publications [1-6], with individually assigned DOI numbers, are available online at:

<https://www.mos-ak.org/munich_2025/>

The development of open-source Process Design Kits (PDKs) is crucial for democratizing access to advanced semiconductor technologies. IHP's OpenPDK initiative bridges the gap between academia, startups, and the semiconductor industry by offering a fully open and manufacturable SG13G2 BiCMOS OpenPDK for analog/RF, mixed-signal, and digital IC applications. Aligning with the EU Chips Act, this initiative emphasizes open collaboration to overcome economic and technical barriers in semiconductor innovation. The workshop introduces SG13G2 OpenPDK and Free and Open-Source Software (FOSS) tools for IC designs, including Verilog-A devices, schematic capture, SPICE simulation, layout, physical verification in advanced design flow up to final typeout.

To learn more about IHP OpenPDK Initiative and its Certified Design Courses, visit online depositories as listed below:

Open-Source Digital Design Course: https://github.com/OS-EDA/Course

• Full RTL-to-GDSII workflow using OpenROAD and SG13G2 PDK
• Feedback integrated via GitHub & live sessions
• Trial run Feb 2025: 15 on-site participants selected from 85+ applicants

Open-Source Analog Design Course: https://github.com/IHP-GmbH/IHP-AnalogAcademy

• Hands-on design with SG13G2 PDK; Strong emphasis on analog/RF practice, focused on the layout and verification, including process variation analysis of analog/RF ICs
• Explored designs: Bandgap, 50 GHz PA, SAR ADC
• Tools: Ngspice, Xyce, Xschem, Qucs, Klayout
• Trial run June 2025: with 16 on-site participants selected from 80+ applicants

MOS-AK Workshop References:

[1] M. Yazici and R. Scholz, "IHP OpenPDK Roadmap", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113282.

[2] Árpád Bűrmen, "The OpenVAF Verilog-A Compilerfor the OpenPDK Ecosystem", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113774.

[3] M. Volker, "User-friendly FDTD EM Workflow for IHP OpenPDK with Automatic Meshing", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113926.

[4] Mike Brinson, "Building Component Libraries for Use with the IHP OpenPDK and FOSS Tools", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113932.

[5] Mirjana Videnović-Mišić, "Analog IC Flow Automatization", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113935.

[6] Ralph Steiner Vanha, "MOS SizingTool – A Single Transistor Simulator", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113946.

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[paper] MicroLEDs SPICE Model

Sultan El Badaoui1,2, Patrick Le Maitre1, Anthony Cibié1, Julia Simon1, Aurélien Lardeau-Falcy1, 

Jeremy Bilde1, Louwenn Cherruault1, Manon Arch1, Michael Pelissier1, Yannis Le Guennec2

SPICE Modeling of GaN MicroLEDs for Optical Communication

Journal of the Society for Information Display, 2025; 0:1–16

DOI 10.1002/jsid.2105

1 Univ. Grenoble Alpes, CEA LETI, Minatec, Grenoble (F)
2 Univ. Grenoble Alpes, CNRS, Grenoble-INP, GIPSA-lab, Grenoble (F)

Abstract: With the rapid expansion of data centers, there is a growing demand for high data-rate, energy-efficient optical links over short distances. One potential technology for this application is Gallium-Nitride (GaN) based microlight emitting diodes (μLEDs), thanks to their compact size, high-speed operation, and ease of manufacturability. During the development of these μLEDs, modeling plays an essential role in optimizing their performance. In this paper, we present various models to estimate both the static and dynamic performance of GaN μLEDs of various sizes. We then propose a methodology to integrate these models into a unified equivalent circuit model, enabling the simulation of the full response of the μLED. Finally, we implement this unified model in a circuit-simulation-compatible module and replicate the experimental setups within a simulation software to evaluate the module's ability to accurately simulate the μLED's response.

FIG: (a) SEM image of a 50-μm μLED, showing the GSG pad configuration and the grid contact over the μLED

(b) Schematic of the stack of the μLEDs 

9c) Simulation setup used to for transient simulation

Acknowledgments: This work is part of the IPCEI Microelectronics and Connectivity and was supported by the French Public Authorities within the frame of France 2030 and by the Institut Carnot CEA-Leti.

[Conference] 33rd Austrochip 2025

Austrochip 2025

33rd Austrian Workshop on Microelectronics

September 25, 2025 – Linz, Austria

The TT workshop program

Conference Program

08:00 – 09:00 Coffee & Registration
09:00 – 09:15 Conference Opening
09:15 – 10:00 First Keynote-Address

• IHP OpenPDK and MPW: Pushing Open-Source EDA tools to Analog and RF Design René Scholz IHP – Leibniz Institute for high performance Microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany

10:00 – 10:45 Second Keynote-Address

• Open-source SoC design using PULP Frank K. Gürkaynak ETH Zürich, IIS, ETZ J 60.1, Gloriastrasse 35, 8092 Zürich, Switzerland

10:45 – 11:00 Break
11:00 – 12:00 Paper Session I:
Session Chair: TBA, TBA

• Gain Expansion Generator based on a Reduced Conduction Angle for H-Band Applications Thomas Ufschlag, Benjamin Schoch, Lukas Gebert, Dominik Wrana, Axel Tessmann and Ingmar Kallfass University of Stuttgart (ILH), Fraunhofer Institute for Applied Solid State Physics IAF
• Greyhound: A Reconfigurable and Extensible RISC-V SoC and eFPGA on IHP SG13G2 Leo Moser, Meinhard Kissich, Tobias Scheipel and Marcel Baunach Graz University of Technology
• Comparison of Low Power Digitally Controlled Ring Oscillator Architectures in 12 nm FinFET Florian Schneider, Luca Avallone and Alicja Michalowska-Forsyth Infineon Technologies Austria AG Institute of Electronics (IFE), Graz University of Technology

12:00 – 12:30 Poster & Sponsor Pitch Session
12:30 – 14:00 Lunch
14:00 – 15:15 Paper Session II:
Session Chair: TBA, TBA

• A 150-GHz 9-dBm EIRP Open-Source FMCW Radar Chip in 130-nm BiCMOS Ghaith Al Sabagh, Georg Zachl and Harald Pretl Institute for Integrated Circuits and Quantum Computing, JKU Linz

• A CMOS Source-Coupled Relaxation Oscillator Achieving Close-in Phase Noise of −72.9 dBc/Hz at a 1 kHz Offset Baset Mesgari, Saeed Saeedi, Reinhard Feger and Horst Zimmermann Institute for Communications Engineering and RF-Systems, Johannes Kepler University Linz Faculty of Electrical and Computer Engineering, Tarbiat Modares University Christian Doppler Laboratory MWTH

• A FR3, 25 dBm Unbalanced MMIC GaAs Doherty Power Amplifier with Auxiliary Gate Voltage Modulation for Linearity Improvement Abdolhamid Noori, Fatemeh Abbassi, Christoph Wagner, Christian Fager and Gregor Lasser Chalmers University of Technology, Silicon Austria Labs

• A 72.7-90.4 GHz VCO with a Stacked NMOS based Tuning Network in 28nm FDSOI Waseem Abbas, Samir Aziri and Christoph Wagner Silicon Austria Labs

• A D-Band Active Down-Conversion Mixer with 80 GHz IF for FMCW Radar Frequency Extension Fatemeh Abbassi, Samir Aziri, Waseem Abbas, Christoph Wagner and Timm Ostermann Silicon Austria Labs, Institute for Integrated Circuits and Quantum Computing, JKU Linz

15:15 – 15:30 Break
15:30 – 16:45 Paper Session III:
Session Chair: TBA, TBA

• Design Automation of a Digitally Controlled Ring Oscillator using CUAS Cell Creator Framework Daniel Cerdà Holmager, Santiago Martin Sondón, Violeta Petrescu, Wolfgang Scherr and Johannes Sturm Carinthia University of Applied Sciences in Austria, CUAS
• Event-Based ADCs vs. Nyquist ADCs: Rethinking Performance Metrics Simon Dorrer, Anna Werzi, Bernhard A. Moser, Michael Lunglmayr and Harald Pretl Institute for Integrated Circuits and Quantum Computing, JKU Linz Institute of Signal Processing, JKU Linz
• Modeling Location-dependent Random Telegraph Noise for Circuit Simulators Florian Berger, Gerhard Landauer, Alicja Michalowska-Forsyth, Martin Flatscher, Philipp Greiner and Stefan Gansinger Institute for Electronics, Graz University of Technology Power and Sensor Systems, Infineon Technologies
• An 8.1-µW 12-bit Non-Binary Self-Clocked SAR-ADC in 130 nm Open-Source PDK Ali Olyanasab, Patrick Fath, Leonhard Schreiner, Christoph Guger and Harald Pretl g.tec medical engineering GmbH Institute for Integrated Circuits and Quantum Computing, JKU Linz
• SPAD Active Quenching/Resetting Circuit in 0.35-µm HV-CMOS Enabling 24V Excess Bias for PDP >90% Sherwin Nasirifar, Baset Mesgari, Christoph Ribisch, Saman Kohneh Poushi and Horst Zimmermann Institute of Electrodynamics, Microwave and Circuit Engineering, TU Wien Institute for Communications Engineering and RF Systems, JKU Linz Austrian Institute of Technology (AIT), Vienna Silicon Austria Labs

16:45 – 17:00 Conference Closing, Best Paper Award & Outlook Austrochip 2026