Recent Compact Modeling Papers

[1] Hao Su, Yunfeng Xie, Yuhuan Lin, Haihan Wu, Wenxin Li, Zhizhao Ma, Yiyuan Cai, Xu Si, Shenghua Zhou Guangchong Hu, Yu He Feichi Zhou, Xiaoguang Liu, Longyang Lin, Yida Li, Hongyu Yu, and Kai Chen; "Characterizations and Framework Modeling of Bulk MOSFET Threshold Voltage Based on a Physical Charge-Based Model Down to 4 K." In 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), pp. 733-736. IEEE, 2024. doi: 10.1109/ESSERC62670.2024.10719583

[2] Tung, Chien-Ting, Sayeef Salahuddin, and Chenming Hu; "A SPICE-Compatible Neural Network Compact Model for Efficient IC Simulations." In 2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 01-04. IEEE, 2024.

[3] Jana, Koustav, Shuhan Liu, Kasidit Toprasertpong, Qi Jiang, Sumaiya Wahid, Jimin Kang, Jian Chen, Eric Pop, and H-S. Philip Wong; "Modeling and Understanding Threshold Voltage and Subthreshold Swing in Ultrathin Channel Oxide Semiconductor Transistors." In 2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 01-04. IEEE, 2024.

[4] Manganaro, Gabriele. "Rethinking mixed-signal IC design." In 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), pp. 552-556. IEEE, 2024

[5] Wager, John F., Jung Bae Kim, Daniel Severin, Zero Hung, Dong Kil Yim, Soo Young Choi, and Marcus Bender; "Dual-Layer Thin-Film Transistor Analysis and Design." IEEE Open Journal on Immersive Displays (2024).

[paper] FOSS support for CM with Verilog-A

Bűrmen, Árpád, Tadej Tuma, Iztok Fajfar, Janez Puhan, Žiga Rojec, Matevž Kunaver

and Sašo Tomažič

Free software support for compact modelling with Verilog-A

Informacije MIDEM 54, no. 4 (October 9, 2024)

<https://ojs.midem-drustvo.si/index.php/InfMIDEM/article/view/1999>

Abstract: Verilog-A is the analog subset of Verilog-AMS - a hardware description language for analog and mixed-signal systems. Verilog-A is commonly used for the distribution of compact models of semiconductor devices. For such models to be usable a Verilog-A compiler is required. The compiler converts the model equations into a form that can be used by the simulator. Such compilers have been supplied with commercial simulators for many years now. Free software alternatives are much more scarce and limited in the features they offer. The paper gives an overview of Verilog-A, Free software Verilog-A compilers, and Free software/Open source simulators that can simulate compact models defined in Verilog-A. Advantages and disadvantages of individual compilers and simulators are highlighted.

Tab: Comparison of Free software simulators

Asterisk denotes a feature under development as of Sep. 2024

Acknowledgements: This research was funded in part by the Slovenian Research Agency within the research program ICT4QoL—Information and Communications Technologies for Quality of Life, grant number P2-0246.

ROSMD 2024 Workshop

Advancing to the Fifth Milestone

ROSMD 2024

Professional Development Program

(HYBRID MODE)

on

RESEARCH OPPORTUNITIES IN SEMICONDUCTOR

MATERIALS AND DEVICES

(ROSMD)

18-23 October 2024

in association with

JOINTLY ORGANIZED BY

Department of Electronics and Communication Engineering

SRM Institute of Science and Technology (SRMIST),

Kattankulathur, Chennai

&

Indian Institute of Information Technology

Design and Manufacturing (IIITD&M),

Kancheepuram

ABOUT THE ROSMD 2024 PROGRAM 

Electronic devices serve as essential components in a wide range of applications. Recently, new semiconductor materials and devices have emerged as revolutionary technologies, leading the international research community. These advancements are driving the development of submicron technologies, reducing costs, and supporting key industries such as electronic information, energy, aerospace, and environmental protection. India has been actively involved in the semiconductor field for decades, with a history that dates back to notable scientists like Sir C. V. Raman and Sir J. C. Bose. Today, India is home to numerous research groups and VLSI foundries that significantly contribute to the global semiconductor landscape. The recent adoption of new materials and technologies has further enhanced the performance of semiconductor devices, allowing for a broader range of applications. In line with India's Atmanirbhar Bharat policy and semiconductor mission, many organizations are working towards the development of indigenous semiconductor technologies. This course aims to shed light on the current status and future potential of semiconductor materials and devices, both in India and around the world  <Read more...> 

REGISTRATION DETAILS

You are required to apply online using the following link

https://forms.gle/15kGBSkPwjcWkcg

or scan QR Code: 

PATRONS

Dr. T.R. Parivendhar, Founder Chancellor, SRMIST

Dr. Ravi Pachamoothoo, Pro-Chancellor (Admin.), SRMIST

Dr. P. Sathyanarayanan, Pro-Chancellor (Academics), SRMIST

ADVISORY COMMITTEE

Prof. C. Muthamizhchelvan, Vice Chancellor,SRMIST

Dr. S. Ponnusamy, Registrar, SRMIST

Dr. T. V. Gopal, Dean CET, SRMIST

Dr. K. Vijayakumar, Dean SEEE, SRMIST

STEERING COMMITTEE

Dr. M. Sangeetha, Professor and Head, ECE, SRMIST, KTR

Dr. B. Ramachandran, Professor, ECE, SRMIST, KTR

Dr. R. Kumar, Professor, ECE, SRMIST, KTR

Dr. S. Malarvizhi, Professor, ECE, SRMIST, KTR

Dr. P. Aruna Priya, Professor, ECE, SRMIST, KTR

Dr. T. Rama Rao, Professor, ECE, SRMIST, KTR

Dr. Shanthi Prince, Professor, ECE, SRMIST, KTR

CONVENER

Dr. Rajesh Agarwal, SRMIST, KTR

Dr. Soumyaranjan Routray, SRMIST, KTR

Dr. K P Pradhan, IIITD&M, Kancheepuram

COORDINATORS

Dr. Sounik Kiran Kumar Dash, SRMIST, KTR

Dr. Sanjay Kumar Sahu, SRMIST, KTR

Dr. Uday Kumar Singh, SRMIST, KTR

Dr. Ferents Koni Jiavana K, SRMIST, KTR

ORGANIZING COMMITTEE

Dr. Kasthuri Bha J.K

Dr. Damodar Panigrahy

Dr. Sandeep Kumar P

Dr. Prithiviraj Rajalingam

Dr. Praveen Kumar S

Dr. Bashyam S

Mr. Muthukumaran B

Mr. Ananda Venkatesan

Dr. Arijit Bardhan Roy

Dr. Md Jawaid Alam

Dr. Vivek Kachhatiya

Dr. Tulika Srivastava

Dr. Sayantani Bhattacharya

Dr. Veer Chandra

Dr. Vishvas Kumar

[mos-ak] [online publications] MOS-AK/ESSERC Workshop in Bruges (B) September 9, 2024

The MOS-AK Association has organized is consecutive 21st ESSERC compact/SPICE modeling workshop, to discuss status of the device level modeling and analog/RF and digital FOSS CAD/EDA IC design tools supporting IHP OpenPDK Initiative. All the recent MOS-AK presentations are available online:

• MOS-AK/ESSERC Workshop in Bruges (B) <https://mos-ak.org/bruges_2024/>

The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and panel discussions around the globe thru the 2024 Year, including:

• MOS-AK Brazil Panel (BR), Oct. 2024
  
• 17th US MOS-AK Workshop, Silicon Valley (US) Dec.11, 2024
• in the timeframe of CMC and IEDM Meetings

W.Grabinski on the behalf of International MOS-AK Committee

WG170924

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/mos-ak/CALp-Rj-U%2BfGZB6xvwZ%3Du_3nVqNY9QitXqwu2CG96dvaZz9avZw%40mail.gmail.com.

[Balloting] IEEE Annual Election: Division I Candidates

IEEE Annual Election: Division I Candidates

Below are the candidates for 2025 IEEE Division I Delegate-Elect/Director-Elect.

The candidates are listed in a pre-determined lottery order and indicates no preference.

• Amara Amara (Nominated by IEEE Division I)
• Fernando J. Guarin (Nominated by IEEE Division I)

Division I Societies:

• Circuits and Systems Society
• Electron Devices Society
• Solid-State Circuits Society

View position description

Balloting for the 2024 IEEE Annual Election has begun. 

The deadline to cast your vote is 

• 12:00 noon ET (16:00 UTC-04) on 1 October 2024.