Apr 29, 2025
[paper] Avalanche Multiplication in SiGe HBTs
Apr 26, 2025
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Apr 25, 2025
[C4P] Micro-Nano 2025
International Conference on Micro- and Nanoelectronics, Nanotechnology and MEMS (MicroNano 2025)
This annual Micro-Nano 2025 conference is organized by the Micro&Nano Scientific Society of Greece and aims to connect people from academia, research and industry, so as to stimulate discussions on the latest scientific achievements and to further promote micro- and nanotechnologies. The conference is held every time in a different city all around Greece, with the most recent one realized in Lemnos (2024). This year's Conference will be held on the island of Crete and is co-organized with the Technical University of Crete.
ABSTRACT SUBMISSION- Conference Dates: November 6-9, 2025
- Submission Opens: will be announced
- Abstract Submission Final Deadline: will be announced
- Peer reviewing will follow immediately after submission.
Apr 24, 2025
[paper] Compact OTM-RRAM Characterization Platform
Abstract: Emerging non-volatile memories (eNVMs) such as resistive random-access memory (RRAM) offer an alternative solution compared to standard CMOS technologies for implementation of in-memory computing (IMC) units used in artificial neural network (ANN) applications. Existing measurement equipment for device characterisation and programming of such eNVMs are usually bulky and expensive. In this work, we present a compact size characterization platform for RRAM devices, including a custom programming unit IC that occupies less than 1 mm2 of silicon area. Our platform is capable of testing one-transistor-one-RRAM (1T1R) as well as one-transistor-multiple-RRAM (1TNR) cells. Thus, to the best knowledge of the authors, this is the first demonstration of an integrated programming interface for 1TNR cells. The 1T2R IMC cells were fabricated in the IHP's 130 nm BiCMOS technology and, in combination with other parts of the platform, are able to provide more synaptic weight resolution for ANN model applications while simultaneously decreasing the energy consumption by 50%. The platform can generate programming voltage pulses with a 3.3 mV accuracy. Using the incremental step pulse with verify algorithm (ISPVA) we achieve 5 non-overlapping resistive states per 1T1R device. Based on those 1T1R base states we measure 15 resulting state combinations in the 1T2R cells.
Apr 23, 2025
[mos-ak] [Announcement] MOS-AK INAOE Workshop, Puebla (MX), May 14-16, 2025
The mail goal of MOS-AK INAOE workshop is to expound on the available free open source tools for each IC development step in the design, simulation and manufacturing of integrated circuits, as well as presenting the options for the fabrication of ICs.
It is very important to train people, build the semi workforce with the basic knowledge needed to grow the semiconductor industry in Mexico. Professionals, including international researchers and experts from INAOE and other institutions, will give talks and courses to explain the tools, their potential uses, showing the engineering requirements and IC design applications.
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