[webcast] Open Source at CERN

CERN Open Source Community Event 2026

Topics included open chips and open FOSS EDA/CAD tools used to design them, with the status update of the open-source ecosystem that supports this work. The impact of AI on free and open-source software communities was also discussed. Updates on recent activities and future plans from the CERN Open Source Program Office (OSPO) were presented. Feedback, ideas, concerns, and suggestions from participants were shared during the discussions.

Community projects and experiences were highlighted through a series of lightning talks. Open-source work from different groups was showcased, creating opportunities for knowledge exchange and new collaborations. The event provided a forum for discussion, community engagement, and the sharing of ideas across the open-source ecosystem.

Agenda November 13, 2026, at CERN
<https://indico.cern.ch/event/1709015/overview>

14:00-14:05 Giacomo Tenaglia: Welcome!

 
14:05-14:25 René Scholz: IHP openPDK, openADK and open-silicon MPW Offerings

14:35-14:55 Frank Gürkaynak: Open-source EDA for chip design: where are we now, what is next?

15:05-15:25 Mathias Schindler: Standing on the shoulders of giants. In winter. During a storm. With sharks.

15:35-16:00 Coffee break

 
16:00-16:20 Lucas Nussbaum: AI-assisted software engineering and Free Software communities:
Tool of liberation or existential threat?

16:30-16:35 Tomas Roun: CPython in the era of AI slop

16:35-16:40 Elena de la Fuente Garcia: “Wakis”: An open-source 3D time-domain electromagnetic solver for beam-coupling impedance simulations

 
16:40-16:45 Benoit Denkinger: SoCMake: a unified build tool for SoC hardware and software

 
16:45-16:50 Anastasiia Petrovych: PQuantML: A Tool for End-to-End Hardware-aware Model Compression

 
16:50-16:55 Dimitrios Danopoulos: AIE4ML: An AI Compiler for Low-Latency Neural Network Inference on AMD Versal AI Engines

16:55-17:00 Sanjiban Sengupta: SOFIE: Optimized and portable ML Inference across heterogeneous architectures

 
17:00-17:20 OSPO 2026 and 2027

 

17:20-17:30 Feedback and discussion

 
17:30-18:20 Feedback, discussions, networking: food and drinks for everyone!

[paper] EKV-gm/ID Design Procedure

Marcello De Matteis

MATLAB-Assisted EKV-gm/ID Design Procedure for Two-Stage Miller-Compensated CMOS OTAs Starting from Closed-Loop Specifications

Journal of Low Power Electronics and Applications 16, no. 4: 53

DOI: 10.3390/jlpea16040053

Department of Physics, University of Milano Bicocca, Piazza della Scienza 3, 20126 Milano, Italy

Abstract: This paper presents a MATLAB-assisted EKV–gm/ID methodology for the systematic synthesis of fully differential two-stage Miller-compensated CMOS OTAs. A sensitivity-based analysis maps the required closed-loop gain, bandwidth, and noise into OTA-level targets. An EKV-inspired analytical model, independently calibrated for nMOS and pMOS devices, provides continuous ID/W, gm/W and gm/ID characteristics with errors below 5% in the design region. Noise-driven sizing explicitly accounts for the different carrier mobilities of the pMOS differential pair and nMOS active load. Transistor parasitic capacitances are estimated from bias-dependent Cgg–VGS characteristics, thereby capturing the reduced gate capacitance of devices operating in moderate or weak inversion. The framework automatically generates transistor dimensions, bias conditions, and Miller-compensation components. These parameters are transferred directly from MATLAB to CADENCE without simulator-assisted resizing or optimization, except for width quantization into 5 μm/300 nm fingers. In 0.18 μm CMOS implementation, MATLAB and nominal commercial CAD simulations predict, respectively, 61.80 and 59.27 dB DC gain, 430.78 and 431.52 MHz unity-gain bandwidth, 69.24° and 68.81° phase margin, 5.0 and 5.3 nV/√Hz input-referred noise at 100 MHz, and 1.426 and 1.314 mW core power. Robustness is assessed over 45 process-voltage-temperature corners, where the nominal solution remains close to the center of the evaluated performance distributions. The results confirm accurate nominal prediction and stable transistor-level behavior across PVT conditions and demonstrate that the proposed methodology accurately designs the OTA operating point, small-signal dynamics, and noise behavior, enabling transistor-level sizing directly from system-level specifications without iterative simulator-assisted optimization.

FIG.1: From Closed-Loop Specifications to a PVT-Verified OTA; MATLAB-Assisted EKV gm-ID Synthesis without Iterative Transistor Level Optimization

FIG.2: Design flow-chart for the two-stage Miller-compensated OTA.

First OpenSUSI MPW

1st OpenSUSI MPW Typeout

Junichi Okamura, Representative Director of OpenSUSI

In October 2025, OpenSUSI, in collaboration with Tokai Rika Co., Ltd., announced the disclosure of PDK information related to the company's 1μm CMOS process. Subsequently, created an environment for open source PDK in OpenSUSI's GitHub repository [1], and launched the open-source semiconductor manufacturing shuttle service "OpenSUSI-MPW" through OpenSUSI's website [1].

For this first OpenSUSI-MPW, by the application deadline on September 18, we received a total of 49 applications from companies, schools, and individuals, exceeding expectations. Users are not limited to individual designers; multiple private companies also use it as a practical tool for developing semiconductor design talent within their in-house structures. In addition, we received two applications for two slots from DX High Schools (key semiconductor schools), as well as many applications from several technical colleges and universities to utilize these slots in semiconductor design education. The manufactured chips are scheduled to be delivered to users around February 2027.

The main goal of OpenSUSI-MPW is not only to establish an open PDK and design environment, but also to provide an environment where everyone can experience manufacturing semiconductors they actually design and actually handling them as actual chips. This first session was the first achievement in which the environment was actually utilized by a diverse range of users, from high schools to companies.

[read more...]

REF:
[1] https://github.com/OpenSUSI/TR-1um
[2] https://www.opensusi.org/mpw-service
[3] YouTube Channel "Ichiken / ICHIKEN": https://www.youtube.com/c/ICHIKEN-video
[4] Recent Invited OpenSUSI Conference Presentation 

IEEE ICTA Special OpenPDK Session; October 22, 2026, Singapore

Contact Information:

General Incorporated Association OpenSUSI

Junichi Okamura (Representative Director)

[ICTA] Special OpenPDK Session

 

The EDS Distinguished Lecturer (DL) Program helps local chapters connect with internationally recognized experts, educators, and authors in the field of electron devices. Through this program, chapters can invite distinguished speakers to deliver high-quality technical lectures and share their knowledge with students, researchers, and industry professionals. The program supports IEEE EDS mission to promote its technical activities, encouraging active participation and IEEE EDS membership, and strengthening local EDS chapters around the world. By bringing leading experts directly to local communities, the DL Program helps foster professional development, knowledge exchange, networking, and greater engagement within the electron devices community.

Wladek Grabinski, IEEE EDS Distinguished Lecturer, visited Singapore recently, it was it was unique opportunity to meet local EDS chapters and the experts in the field of electron devices. 

Here with Yawei Li, Nanyang Assistant Professor at School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore. Previously, Prof. Li was a Lecturer at ETH Zürich, where he worked with Prof. Luca Benini. Prof. Li research focuses on AI efficiency, aiming to accelerate computation, reduce memory footprint, and mitigate power consumption in AI systems. His R&D group research improves AI model efficiency, maps AI models onto targeted hardware, and designs AI hardware to serve AI models for vision, language, and robotic tasks (see: https://ofsoundof.github.io/)

Following meeting at A*Star in Singapore was hosted by Dr. C.C. Ku from the Institute of Microelectronics (IME) and the new head of ICDS. It was a unique chance to talk about Compact/SPICE modeling. We also discussed how to make Verilog-A a standard part of the OpenPDK Initiative. Aferward, Kumaran Sundaram, A*Star, has contributed to ICTA2026 Session "Design Automation and Optimization" with talk on "Evidence-Driven PDK-IP Co-Readiness Assessment and Regression Routing Under AutomotiveConstraints"

Prof. Yeo Kiat Seng of the Singapore University of Technology and Design (SUTD), Singapore, and Tianjin University, China, officially opened the 9th IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA 2026), held in Singapore on October 21-23, 2026. The conference provided an international IEEE forum for researchers, engineers, students, and industry professionals to present and exchange the latest developments in integrated circuit design, semiconductor technologies, and emerging applications. It also encouraged collaboration across different disciplines to address the challenges of our rapidly changing technological society. During his opening remarks, Prof. Yeo highlighted the growing importance of the OpenPDK initiative and the increasing adoption of FOSS CAD/EDA tools for integrated circuit design. He emphasized the value of these open technologies for both academic research and industrial innovation, helping to make advanced IC design more accessible to a broader community. With the personal support of Prof. Yeo and the full endorsement of the ICTA Organizing Committee, the conference program included a Special OpenPDK Session, providing a dedicated platform to discuss recent progress, challenges, and opportunities in open-source design technologies and ecosystem development. The Special Session coordinated by local Singapore Section RL07/EP21/ED15 Joint Chapter was open to all the IEEE EDS members.

Special Session “OpenPDK - Global FOSS Scholar Platform" Program

T_1	SPICE/Verilog-A Standard Model and OpenPDK Practice Wladek Grabinski, IEEE EDS DL, MOS-AK (EU) IHP OpenPDK (D)
T_2	Open-Source Ecosystem Updates and Semiconductor Design Development Programs in Japan Jun-ichi Okamura, AIST Solutions, OpenSUSI (J)
T_3	Open-Source EDA Meets Industrial IC Design Ehrenfried Seebacher, ams-OSRAM AG (A)
T_4	Building an Open-Source Process Platform, Empowering VLSI Innovation and Development Da Zhang Zhejiang University/CTO, Zhejiang Chuangxin Integrated Process Platform (CN)
T_5	From Silicon to Design: Intelligent Measurement and Modeling for DTCO Yutao Ma, VP of R&D, Primarius Technologies. Ltd. (CN)
T_6	Beyond Moore, Application-Driven IC Innovation International Cooperation Opportunities at NICE Alex Gu, National Innovation Center Par Excellence (NICE) (CN)
T_7	2.5D/3D IC: AI+EDA Reshaping the System-Design-Technology Co-Optimization (STCO) Paradigm for Advanced Packaging Alex Zhao, Founder/CEO Zhuhai SiChip Technology Co., Ltd. (CN)
T_8	Modelling of semiconductor devices: the heart of innovation bridging academia and industrial applications Fujiang Lin, University of Science and Technology of China (USTC) (CN)

[MOS-AK] ESSERC W7 Workshop in Palma

Synopsys: The 23rd MOS-AK/ESSERC Compact Modeling Workshop in Palma de Mallorca brings together the international community advancing SPICE/Verilog-A modeling, OpenPDKs, and open-source IC design flows. Since 2002 ESSEDRC/ESSCIRC in Porto, MOS-AK has been the leading forum connecting technology developers, circuit designers, and FOSS CAD/EDA contributors, supporting knowledge exchange and strengthening the open semiconductor ecosystem. This year's program showcases cutting-edge developments: GaN MOS-HEMT compact models for emerging OpenPDKs, AI/ML-driven modeling workflows replacing manual tuning, cryogenic FD-SOI model libraries, fully open-source RFIC design case studies using IIC-OSIC-TOOLS, reliability insights for advanced CMOS and RF technologies, and a new OpenPDK MOSFET matching matrix IC enabling fast mismatch characterization. The workshop organizers are inviting engineers, researchers, and students who want a clear, practical view of modern device models and open simulation frameworks. It directly supports global OpenPDK adoption and aligns with European ODE4EC-AMS activities, promoting accessible, reproducible, and future-ready IC design methodologies.

9:30 - 11:00	W7 Workshop Opening
T_1	ODE4EC-AMS OpenPDK: the Status and Roadmap Wladek Grabinski IHP OpenPDK (D)
T_2	Advances in Open-Source Verilog-A Compilation and Simulatio> Arpad Buermen Uni. Ljubljana (SL)
T_3	Compact Modeling of GaN MOS-HEMTs for Open PDKs Ashkhen Yesayan EPFL (CH)
T_4	From Manual Tuning to Agentic AI: Transforming Device Modeling with AI/ML Roberto Tinti Keysight (US)
11:00 - 11:30	Coffee Break
T_5	Development of Cryogenic Model Libraries for FD-SOI Transistors Phanish Chava AdMOS (D)
T_6	Open-Source RFIC Design: Case Studies Using IIC-OSIC-TOOLS Georg Zachl JKU Linz (A)
T_7	Reliability topics for the miniaturization and qualification and OpenSilicon perspective Fernando Guarin IEEE EDS D1 (US)
P_1	[Poster] OpenPDK MOSFET Matching Matrix IC Juan Brito CEITEC (BR)
SSCS	Code-a-Chip Award Ceremony Akira Tsuchiya SSCS TC-OSE
13:00-14:00	End of the W7 Workshop and Lunch Break

The MOS-AK workshop was followed by ESSERC W2 Joint Workshop FAMES Pilot Line and SiNANO Institute reviwing the FDSOI Pilot Line Insights and Perspective. W2 was the first to present in-depth technical results obtained through the FAMES Pilot Line project on the development of FD-SOI at 10nm and 7nm nodes, combined with non-volatile memories (NVM) and 3D options, RF components and smart PMIC (Power Management Integrated Circuit), providing a pathway to deliver high-performance, low-power consumption solutions for future chips.

With the highlight talk: Next generations of FD-SOI technology for low-power and RF applications

by Thierry Poiroux (CEA-Leti, FR) and Valeriya Kilchytska (UCLouvain, BE)