Nov 6, 2025

[Book] Essential Semiconductor Physics

Essential Semiconductor Physics
Mark Lundstrom (Purdue University, USA)
New Era Electronics: A Lecture Notes Series
Pages: 424; October 2025
https://doi.org/10.1142/14454

This book is the fourth volume in the New Era Electronics lecture notes series, a compilation of volumes defining the important concepts tied to the electronics transition happening in the 21st century.
The lectures in this volume are about the underlying physics that makes semiconductor devices possible. The treatment is physical and intuitive; the text is descriptive, not heavily mathematical. The lectures are designed to be broadly accessible to students in science or engineering and to working engineers. They present an electrical engineering perspective, but those in other fields may find them a useful introduction to the approach that has guided the development of semiconductor technology for more than 75 years.
For those who use semiconductor devices, these lectures provide an understanding of the physics that underlies their operation. For those developing semiconductor technologies, these lectures provide a starting point for diving deeper into the physics, chemistry, and materials science relevant to semiconductors. Those who have taken advanced courses will see how specific topics fit into a broader framework. 

Book Sections

Front Matter; pp. i–xvi

Part 1: Materials Properties and Doping
  • Lecture 1: Energy Levels to Energy Bands; pp. 3–16
  • Lecture 2: Crystalline, Polycrystalline, and Amorphous Semiconductors; pp. 17–27
  • Lecture 3: Miller Indices; pp. 29–39
  • Lecture 4: Properties of Common Semiconductors; pp. 41–46
  • Lecture 5: Free Carriers in Semiconductors; pp. 47–56
  • Lecture 6: Doping; pp. 57–75
Part 2: Rudiments of Quantum Mechanics
  • Lecture 7: The Wave Equation; pp. 79–99
  • Lecture 8: Quantum Confinement; pp. 101–116
  • Lecture 9: Quantum Tunneling and Reflection; pp. 117–129
  • Lecture 10: Electron Waves in Crystals; pp. 131–145
  • Lecture 11: Density of States; pp. 147–164
Part 3: Equilibrium Carrier Concentrations
  • Lecture 12: The Fermi Function; pp. 167–177
  • Lecture 13: Fermi-Dirac Integrals; pp. 179–190
  • Lecture 14: Carrier Concentration vs. Fermi Level; pp. 191–203
  • Lecture 15: Carrier Concentration vs. Doping Density; pp. 205–213
  • Lecture 16: Carrier Concentration vs. Temperature; pp. 215–228
Part 4: Carrier Transport, Recombination, and Generation
  • Lecture 17: Current Equation; pp. 231–250
  • Lecture 18: Drift Current; pp. 251–270
  • Lecture 19: Diffusion Current; pp. 271–280
  • Lecture 20: Drift-Diffusion Equation; pp. 281–288
  • Lecture 21: Carrier Recombination; pp. 289–308
  • Lecture 22: Carrier Generation; pp. 309–323
Part 5: The Semiconductor Equations
  • Lecture 23: The Semiconductor Equations; pp. 327–342
  • Lecture 24: Energy Band Diagrams; pp. 343–361
  • Lecture 25: Quasi-Fermi Levels; pp. 363–374
  • Lecture 26: Minority Carrier Diffusion Equation; pp. 375–396
Back Matter; pp. 397–406

Oct 26, 2025

[paper] 28 GHz Wireless Channel for a Quantum Computer at 4K

Ama Bandara∗, Viviana Centritto Arrojo∗, Heqi Deng†, Masoud Babaie†, Fabio Sebastiano†, Edoardo Charbon‡, Evgenii Vinogradov∗, Eduard Alarcon∗, Sergi Abadal∗
28 GHz Wireless Channel Characterization for a Quantum Computer Cryostat at 4 Kelvin
arXiv:2510.16962v1 [quant-ph] 19 Oct 2025

∗Nanonetworking Center in Catalunya, Universitat Politecnica de Catalunya, Barcelona (SP)
† Delft University of Technology (NL)
‡ Ecole Polytechnique F ́ed ́erale de Lausanne (EPFL, CH) 

Abstract: The scalability of quantum computing systems is constrained by the wiring complexity and thermal load introduced by dense wiring for control, readout and synchronization at cryogenic temperatures. To address this challenge, we explore the feasibility of wireless communication within a cryostat for a multi-core quantum computer, focusing on wireless channel characterization at cryogenic temperatures. We propose to place on-chip differential dipole antennas within the cryostat, designed to operate at 28 GHz in temperatures as low as 4 K. We model the antennas inside a realistic cryostat and, using full-wave electromagnetic simulations, we analyze impedance matching, spatial field distribution, and energy reverberation due to metallic structures. The wireless channel is characterized through measured channel impulse response (CIR) across multiple receiver antenna positions. The results demonstrate potential for reliable shortrange communication with high Signal-to-Noise Ratio (SNR) and limited sensitivity to positional variation, at the cost of nonnegligible delay spread, due to significant multipath effects.
Fig: Spatial distribution of the electrical field across the cryostat as observed in the cross-section, 
general top view, and top view at the plane of the antennas.

Acknowledgements: Authors gratefully acknowledge funding from the European Commission via projects with GA 101042080 (WINC) and 101099697 (QUADRATURE).

Oct 16, 2025

[IEEE EDS MQ] Trends and Challenges in Microelectronics

IEEE EDS MQ “Trends and Challenges in Microelectronics
Monday, October 13th, 2025
FACULTY OF ELECTRONIC ENGINEERING
University of Niš
Aleksandra Medvedeva 4, Niš, Serbia
8:00 Registration

8:30   Introductory Remarks and Opening Address
D. Danković, University of Niš, Serbia
Z. Marinković, University of Niš, Serbia

Session I: Chairmen: T. Grasser, V. Davidović

8:45   Device Engineering in E.V.E. Era for Sustainable Nanoelectronics and Nanosystems
S. Deleonibus; CEA/LETI, France


9:10 Neuromorphic Technologies for Autonomous Intelligent Systems at the Edge
[online] A. M. Ionescu; Swiss Federal Institute of Technology, Switzerland

9:30 Coffee break

9:40 Contacts at the Nanoscale and for Nanomaterials
H. Wong; University of Hong Kong, Hong Kong


10:05 Unlocking the Potential of Multifunctional Devices
[online] N. El-Atab; KAUST Saudi Arabia

10:25 Coffee break

Session II: Chairmen: H. Wong, D. Danković

10:35 Steep-slope Devices: Prospects and Challenges
E. Gnani; University of Bologna, Italy

11:00 Modeling FinFETs, Nanowires and Stacked Nanosheets with Temperature
[online] A. Cerdeira; CINVESTAV-IPN, Mexico

11:20 Coffee break

11:30 The IHP OpenPDK Initiative: RoadMap Update
W. Grabinski; IEEE EDS R8 Chair

11:55 A Review of Lambert’s W Function Utilization in Nanodevice Modeling
[online]A. Ortiz-Conde; University Simon Bolivar, Venezuela

12:15 Coffee break

12:25 Benchmarking Insulators for Devices Based on 2D Materials
T. Grasser; Technical University of Vienna, Austria


 


Oct 11, 2025

[Internship] Open Source CAD Design Flows

A great opportunity at CEA-Leti in Grenoble, France! This 6-month internship focuses on open source CAD design flows with related PDK, targeting final-year engineering or Master 2 students with an analog/digital design profile.


Description

Are you eager to explore the backstage of microelectronics and learn how to turn a circuit design into a chip ready for fabrication? This internship invites you to take on an exciting challenge: setting up and running a complete open source design flow on related process technology, using an existing SAR ADC design as a motivating example.

The core mission is not to redesign the ADC, but to master the flow that makes such a design possible: installing the tools, configuring the PDKs, and validating each step of the process. How do you configure and launch open source EDA tools? How do you run simulations, placement and routing, and physical verification checks? What are the strengths and limitations of open source technologies in microelectronics design IC? You will be encouraged to explore these questions and propose your own answers.

  • Starting date: Spring 2026
  • Duration: 5-6 months
  • Location: Grenoble, France

Your main tasks will include:

  • Installing and configuring the open source design environment (PDK, EDA tools, automation scripts).
  • Running the design flow on an existing SAR ADC as a case study.
  • Carrying out simulation, synthesis, place-and-route, and DRC/LVS verification.
  • Identifying bottlenecks and documenting reproducible solutions.

The student will be supported by an experienced team, with close mentoring and external collaborations to enrich your learning. He won't be left alone with the complexity of the flow – he will be guided, encouraged to test, and empowered to take initiatives. Indicative time allocation: ~30% installation and flow automation, 30% simulation and verification, 30% design adaptation, 10% analysis and scientific dissemination.

Candidate Profile

You are a master's student in microelectronics, embedded systems, or related fields. You have basic knowledge in digital/analog design, simulation, or VLSI concepts. You have basic experience writing scripts in bash/csh and are comfortable working in a Linux environment.


Supervisors: 
Youcef Fellah & Guillaume Regis

To apply, please contact: <youcef.fellah@cea.fr>

Oct 9, 2025

[mos-ak] [C4P] ICMTS 2026 Mar. 23-26, 2026 in Matsue, Japan


IEEE International Conference on Microelectronic Test Structures
Mar. 23-26, 2026 at Kunibiki-Messe Convention Center in Matsue, Japan
ICMTS 2026 Call for Papers
Abstract submission deadline: Nov 15, 2025

Looking for the best opportunity to present and discuss your ideas and results about test structures, measurements, and characterization? This is your chance! Join the 38th ICMTS conference.

This conference is co-sponsored by the IEEE Electron Devices Society. All presented papers will be submitted for potential inclusion in IEEE Xplore®. Original papers presenting new developments in topics relevant to ICMTS, include but not limited to test structures, measurements, and results, as outlined below. This one-track technical program will award a Best Paper that will be voted on by the Technical Program Committee. In addition, Tutorial Short Course will precede the main conference while several of the best measurement, equipment design, and manufacturing experts, will participate in the equipment exhibition and presentations.
  • Design
    • Methodologies, Verification
    • Within-die circuits for process characterisation/monitoring
    • Design enablement, characterisation and validation of digital and analog libraries
    • Devices and Circuit Modelling
  • Measurement techniques
    • DC, AC and RF measurements: setup, test and analysis
    • Reliability test - including thermal stability, failure analysis etc.
    • Statistical analysis, variability, throughput increase, smart test strategies
    • Use of machine learning and AI in analysis of data sets - parameter extraction etc.
    • Wafer probing, within-die measurements, in-line metrology
    • Throughput, testing strategies, yield enhancement and process control tests
  • Applications
    • Emerging memory technologies (single cell, arrays, and application in neural networks)
    • Emerging transistor technologies for digital/analog/power applications
    • Photonic devices - silicon integration, new displays (OLED, μ-displays)
    • Flexible electronics and sensors (organic and inorganic materials)
    • M(N)EMS, actuators, sensors, PV cells and other emerging devices
The author's abstract submission consists of up to four pages in PDF format (font-embedded). The first page should include a title, a 50-word summary, author name(s), full address, contact number and e-mail of the lead author, and any preference for oral or poster session presentation. The body of the abstract should consist of one page of text (800 to 1000 words) and up to two pages of major figures and tables.

The selection process will be based on the technical merit and will be highly weighted in favour of abstracts with high test structure content, giving a clear illustration of the test structure and including measurements and data analysis.

Abstract submission deadline: Nov 15, 2025

Notice of paper acceptance will be sent to the selected authors by Jan 17, 2026, with instructions for the expanded manuscript preparation for the conference proceedings. The deadline for submission of the final, camera-ready paper will be Feb 17, 2026.

Please join the ICMTS group at 
if you have interest in all things, test and measurement.

Details of the venue, hotel, conference registration, etc. are available here.

If you have any questions, please contact the Technical Program Chair: