FETCH2026 Program

FETCH2026

4-6 Février 2026

Lavey-les-Bains (Vaud, Suisse)

Purpose: Mastering the heterogeneity of embedded systems through efficient design technologies is an unavoidable challenge for the years to come. To monitor and anticipate the emergence of new techniques for modelling, validating and synthesising these systems, FETCH 2026 aims to bring together and cross-reference expertise in these various facets. It is a unique annual event for scientists and professionals wishing to share and exchange the most recent knowledge in these fields [read more...]

FETCH2026 Program
Time	Speaker	Affiliation	Title
Feb. 4
08:20	Thoma, Upegui, Levisse	—	Introduction
08:30	David Ruffieux	CH-CSEM	Capteurs intelligents sans fil et énergie autonomes
09:20	Antoine Frappé	FR-JUNIA	Ultra-low-power Human Area Network
09:40	Kevin Martin	FR-Université Bretagne Sud	Splitting embarrassingly parallel loops of tinyML applications
10:00	Pause	—
10:30	Damien Querlioz	FR-Université Paris Sud	Memristors pour une IA de confiance
10:50	Jean‑Michel Portal	FR-AMU Marseille	TBD
11:10	Cédric Marchand	FR-EC Lyon	Transistors ferroélectriques & PUF
11:30	Laura Begon‑Lours	CH-ETHZ	Oxydes ferroélectriques pour circuits neuromorphiques
11:50	Repas	—
13:20	Benoit Miramond	FR-Université Côte d’Azur	From Spikes to Silicon
14:10	Eric Fragnière	CH-HEIA‑FR	Implémentation analogique intégrée de SNN
14:30	Léopold Van Brandt	BE-UCL	Excitabilité des neurones à impulsions
14:50	Ma thèse en 180s	—
15:40	Posters / Pause	—
16:25	Jérôme Toublanc	FR-Synopsys	Implémentation multiphysique des semi‑conducteurs
16:45	Bertrand Reulet	CA-Université Sherbrooke	Bruit d’un système non‑linéaire
17:05	Andreas Burg	CH-EPFL	Fin du CMOS SRAM scaling
17:25	Dragomir Milojevic	BE-Université Libre de Bruxelles	3D stacking & CMOS2.0
20:00	Repas	—
Feb. 5
08:30	Jean‑Paul Chaput	FR-LIP6	Coriolis: RTL→GDSII
09:20	Cesar Fuguet	FR-INRIA	Cost of ECC in RISC‑V L1
09:40	Christian Fabre	FR-CEA	RISC‑V, open hardware & open source
10:00	Pause	—
10:30	Sylvain Saïghi	FR-IMS Bordeaux	EU RadioSpin
10:50	Agathe Archet	FR-Thales	HW‑NAS for heterogeneous embedded targets
11:10	David Novo	FR-LIRMM	Systolic arrays for ADAM Edge AI
11:30	Martin Andraud	BE-Université catholique de Louvain	Test & reliability in analog AI accelerators
11:50	Alberto Dassatti	CH-HEIG‑VD	Democratizing NVMe storage research
12:10	Repas	—
13:40	Paolo Maistri	FR-Université Grenoble	Effets des rayons X sur FPGA sécurisés
14:00	Olivier Savry	FR-CEA	Intégrité de calculs processeurs
14:20	Pascal Cotret	FR-ENSTA	Enclave‑aware cache replacement
14:40	Ma thèse en 180 s	—
15:30	Posters / Pause	—
16:20	Thomas Bourgeat	CH-EPFL	Verified OoO execution in dataflow circuits
16:40	Laurent Maillet‑Contoz	FR-STMicroelectronics	Jumeaux numériques
17:00	Laurence Pierre	FR-TIMA	Vérification d’émulation RISC‑V dans QEMU
20:00	Repas	—
Feb. 6
08:30	Benoit Larras	FR-JUNIA	Event‑driven binarized conv layer
08:50	Marina Reyboz	FR-CEA	TBD
09:10	Bertrand Granado	FR-Sorbonne Université	IA médicale & explicabilité
09:30	Ranwa Al Mallah	CA-Collège militaire royal du Canada	Robustesse RL embarqué face aux attaques
09:50	Fatma Jebali	FR-CEA	AI‑driven performance modeling
10:10	Pause	—
10:40	Anna Sfyrla	CH-UNIGE / CERN	FPGAs & Higgs boson
11:30	Quentin Berthet	CH-HEPIA	Accélération du trigger ATLAS
11:50	Felipe Magalhaes	CA-Polytechnique Montréal	Systèmes temps réel partitionnés
12:10	Sébastien Roy	CA-Université de Sherbrooke	ColdHive IoT platform
12:30	Mot de la fin	—
12:40	Repas	—

[Review] Organic Transistors Compact Models

Monideepa Dutta, Nikhil Ranjan Das, Benjamin Iñiguez, Alexander Kloes, Ghader Darbandy

Review of DC and AC Core Compact Models and Device Performance in Organic Transistors 

J. Appl. Phys. 139, 010701 (2026 Open Access)

DOI: 10.1063/5.0303946

1. NanoP, TH Mittelhessen University of Applied Sciences, 35390 Gießen (D)

2. Institute of Radio Physics and Electronics, University of Calcutta, West Bengal (IN)

3. Department of Electronic Engineering, Universitat Rovira i Virgili, 43007 Tarragona (SP)

Abstract: Organic transistors offer lightweight, flexible, and low-cost platforms for large-area electronics, making them particularly attractive for applications in wearables and biosensing. Their effective use requires detailed characterization and accurate simulation, with compact models providing the foundation for predicting device behavior and enabling reliable circuit-level design. Yet, the diversity of organic semiconductors and the complexity of charge transport demand multiple core modeling approaches, each built on distinct physical assumptions. First, this review summarizes reported lateral and vertical organic transistor architectures, outlining their structural principles and material implementations. It then considers core compact physics-based models for both DC and AC operation, emphasizing their formulations, underlying assumptions, and the physical effects they incorporate. Finally, it reviews reported DC and AC characteristics across diverse material systems, with particular attention to bias-normalized parameters that enable consistent and meaningful cross-study comparisons. By exploring existing core models and performance analyses, this review highlights the fundamental physical principles incorporated into reported compact models and bridges device-level physics with application-oriented circuit design. It offers a comparative perspective on modeling strategies suitable for flexible and biointegrated electronics, while identifying key overlaps in the literature and providing a foundational framework for efficient future model development. Additionally, the review underscores the importance of harmonized terminology to accelerate the development of next-generation models and enhance consistency across studies.

Fig : Virtual-source point x0 in the channel, where the carrier charge and velocity are defined, corresponding to the peak of the conduction band profile.

Acknowledgments : The authors would like to acknowledge the funding from the German Research Foundation (DFG) under Grant Nos. “DA 2578/2-1” and “INST169/22-1.”

FreeCAD Beginner's Handbook

FreeCAD Beginner's Handbook by Aleksander Sadowski (Author)

ALSADO Independently Published

Publication Date: Dec. 26, 2025  (English, pp. 293)

ISBN-13: 979-8275865370

https://www.amazon.com/dp/B0G9HXYYGX

Learn 3D Design with FreeCAD Through Real-World Examples and Hands-On Projects

Discover the world of 3D design with FreeCAD, the free and open-source CAD software used by engineers, designers, and makers worldwide. This full-color, practical guide takes you step by step through a reliable modeling workflow, showing you how to create real-world products and inventions and even complete a complex project like designing a Mars Rover from scratch to solidify your knowledge.

Table of Contents

1. Working with 3D Shapes on Paper
2. Getting Started with Solid Modeling Theory
3. Quickstarting FreeCAD with your first 3D CAD Model
4. Creating Sketches using the Sketcher Workbench
5. Creating Parts using the Part Design Workbench
6. Creating Assemblies using the A2Plus Workbench
7. Preparing your FreeCAD Designs for 3D printing
8. Sharing your FreeCAD Designs in the Maker Community
9. Building the Mars Rover in FreeCAD from Scratch

About the author

Aleksander Sadowski is the founder of ALSADO, the world’s first company offering professional FreeCAD support in the industry. He is studying mechanical engineering at the Bonn-Rhein-Sieg University of Applied Sciences and has been actively involved in the FreeCAD community for many years. Aleksander is developing a workflow for product development in mechanical engineering, fully composed of open-source-software, including FreeCAD, LibreOffice, PrePoMax and OpenRadioss. Based on that he is developing an open-source-software to make collaboration in engineering teams more accessible to manufacturing start-ups and small to medium sized enterprises (SMEs).

In the past, Sadowski worked in product safety at the machine manufacturer GROB and at a company, that specializes in developing simulation software for defense applications. He has been collaborating with Altair, the association of German engineers (VDI) and the German space agency (DLR) to promote the use of open-source software in the industry, especially in mechanical engineering, automotive and aerospace. Aleksander Sadowski is the inventor of a safety screw, that he developed with the help of an open-source-workflow.

Through his books, Aleksander aims to reduce the beginner learning challenges and frustration by teaching a systematic process of working with FreeCAD consisting of most-used functions and a standard modeling workflow which he has refined through his years of experience of teaching FreeCAD in a productive and mission-critical environment. The books make this knowledge accessible to everyone, not just the companies.

👉 Get your own copy on Amazon now:

USA: https://lnkd.in/ei85vWje

Germany: https://lnkd.in/e89hRaux

United Kingdom: https://lnkd.in/euTJ-FzV

Poland: https://lnkd.in/eVJt4Nzh

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Netherlands: https://lnkd.in/eNmFJN-M

Japan: https://lnkd.in/eivmSJZp

[Data] CMOS SKY130 Cryo Primitives

Akturk, Akin, Li, Anhang, Saligane, Mehdi, Riem, Joseph, Adam, Gina, Hoskins,

Brian D, Shrestha, Pragya

CMOS SKY130 Primitives measured at cryogenic temperatures

NIST, (2023: Part of CHIPS METIS Data Collection)

Version: 1.1. Revised: 2024-03-27

DOI: 10.18434/mds2-2997 (Accessed 2026-01-03)

Abstract: SKY130 is an open source complementary metal oxide semiconductor (CMOS) technology manufactured by Skywater Technology (SKY) in its facility in Bloomington, Minnesota. Since it is an open source technology, there are no legal restrictions on its characterization, unlike in typical foundry semiconductor technologies. To facilitate the development of cryogenic electronics, this data set includes measurements of devices manufactured in SKY130 at low temperatures.

Fig: NIST Cryo Circuit Module Description

Name	File Type	Size
2997_README_v4.txt	Plain text	4.46 kB
ETest Tile.zip	Compressed file archive	3.81 MB
MPW-5 Test Tile.zip	Compressed file archive	39.5 MB

[paper] Channel-last GAA nanosheet oxide FETs

Fabia F. Athena, Xiangjin Wu, Nathaniel S. Safron, Amy Siobhan McKeown-Green, Mauro Dossena, Jack C. Evans, Jonathan Hartanto, Yukio Cho, Donglai Zhong, Tara Pena, Paweł Czaja, Parivash Moradifar, Paul C. McIntyre, Mathieu Luisier, Yi Cui, Jennifer A. Dionne, Greg Pitner, Iuliana P. Radu, Eric Pop, Alberto Salleo, H.-S. Philip Wong

Channel-last gate-all-around nanosheet oxide semiconductor transistor

arXiv:2512.21330v1 [cond-mat.mtrl-sci] 24 Dec 2025

1. Department of Electrical Engineering, Stanford University, Stanford (US)
2. Corporate Research, Taiwan Semiconductor Manufacturing Company, Ltd., San Jose (US)
3. Department of Chemistry, Stanford University, Stanford (US)
4. Department of Information Technology and Electrical Engineering, ETH Zurich (CH)
5. Department of Material Science and Engineering, Stanford University, Stanford (US)
6. Department of Chemical Engineering, Stanford University, Stanford (US)
7. Applied Energy Division, SLAC National Accelerator Laboratory, Menlo Park (US)
8. Institute of Metallurgy and Materials Science, Polish Academy of Sciences (PL)
9. Corporate Research, Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)

Abstract: As we move beyond the era of transistor miniaturization, back-end-of-line compatible transistors that can be stacked monolithically in the third dimension promise improved performance for low-power electronics. In advanced transistor architectures, such as gate-all-around nanosheets, the conventional channel-first process involves depositing dielectrics directly onto the channel. Atomic layer deposition of gate dielectrics on back-end-of-line compatible channel materials, such as amorphous oxide semiconductors, can induce defects or cause structural modifications that degrade electrical performance. While post-deposition annealing can partially repair this damage, it often degrades other device metrics. We report a novel channel-last concept that prevents such damage. Channel-last gate-all-around self-aligned transistors with amorphous oxide-semiconductor channels exhibit high on-state current (> 1mAμm) and low subthreshold swing (minimum of 63mV/dec) without the need for post-deposition processing. This approach offers a general, scalable pathway for transistors with atomic layer deposited channel materials, enabling the future of low-power three-dimensional electronics.

Fig: Electrical performance of CL GAA FETs. (A) A SEM image of a representative device structure and (B) an AFM image of IWO deposited on a control sample show a uniform and smooth surface.  (C) IdVgs for a CL GAA FET with tch = 6nm measured at VDS = 0.05V and 1V. (D) IdVgs for a CL GAA FET with tch = 9 nm measured at VDS = 0.05V and 1V. Dual sweep shows very low hysteresis of about 0.038V at VDS = 0.05V.

Acknowledgment: Supported in part by SRC JUMP 2.0 PRISM and CHIMES Center, Stanford Differentiated Access Memory (DAM), SystemX Alliance, Stanford NMTRI, TSMC-Stanford Joint Development Project (P.C.M.). Part of this work was performed at Nano at Stanford (RRID SCR 026695). Authors acknowledge help and support for the AFM measurements from Christina Newcomb. Stanford authors thank MSS USA Corp. for high quality TEM sample preparation and examination and Dr. David Fried of Lam Research for providing access to Coventor SEMulator3D for process simulation. Use of the Stanford Synchrotron Radiation Lightsource at SLAC National Accelerator Laboratory is supported by the U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences under Contract No. DE-AC02-76SF00515. Y.C. acknowledges the support from the Japan Society for the Promotion of Science (JSPS) overseas research fellowship. J.A.D., A.M.G., and P.M. acknowledge the financial support from the U.S. Department of Energy Office of Science National Quantum Information Science Research Centers as part of the Q-NEXT center. Y.C. and F.F.A. would like to thank the support from the Stanford Energy Postdoctoral Fellowship and Precourt Institute for Energy.