[paper] SEMIDV Device Simulator with Quantum Effects

Chien-Ting Tung

SEMIDV: A Compact Semiconductor Device Simulator with Quantum Effects

ArXiv preprint arXiv:2504.00214 (2025)

Abstract: In this paper, I present SEMIDV – a compact semiconductor device simulator incorporating quantum effects. SEMIDV solves the Poisson-Drift-Diffusion equations for semiconductor devices and provides a user-friendly Python interface for scripting and data analysis. Localization landscape theory is introduced to provide quantum corrections to the Drift- Diffusion equation. This theory directly solves the ground state of the Schrödinger equation without further approximation, offering an efficient solution for quantum effect modeling. Additionally, a compact mobility model considering ballistic transport is developed to capture the ballistic length dependence of mobility and the velocity overshoot effect in short-channel devices. Finally, a study on a nanosheet FET using SEMIDV is conducted. I analyze the electrical characteristics of a state-of- the-art GAA/RibbonFET with a 6 nm gate length and discuss the effects of velocity overshoot and quantum confinement on currents and capacitances. A design for an ultra-short-channel transistor with a gate length down to 4.5 nm with a Vdd = 0.45 V is proposed to push the boundaries of integrated circuit technology further.

FIG: Silicon 6nm RibbonFET CMOS structure for SIMIDV calibration 

[Session] Improving Chip Design Enablement for Universities in Europe

DATE2025 FS06 Focus Session:

Improving Chip Design Enablement for Universities in Europe

Date: Tuesday, 01 April 2025

Time: 11:00 CEST - 12:30 CEST

Location / Room: Rhône 1

Session chair:
Ulf Schlichtmann, TU Munich, DE

Session co-chair:
Holger Blume, Leibniz University Hannover, DE

Organisers:
Norbert Wehn, University of Kaiserslautern-Landau, DE
Lukas Krupp, University of Kaiserslautern-Landau, DE

Time	Label	Presentation Title Authors
11:00 CEST	FS06.1	PANEL: IMPROVING CHIP DESIGN ENABLEMENT FOR UNIVERSITIES IN EUROPE Speaker : Norbert Wehn, RPTU University of Kaiserslautern-Landau, DE Authors : Matthew Venn 1 , Joachim Rodrigues 2 , David Atienza 3 , Ian O'Connor 4 , Andreas Brüning 5  and Patrick Haspel 6 1 Tiny Tapeout, ES;  2 Lund University, SE;  3 EPFL, CH;  4 Lyon Institute of Nanotechnology, FR;  5 FMD, DE;  6 Synopsys, DE Abstract The semiconductor industry is central to the European economy, particularly in the industrial and automotive sectors. Semiconductor fabrication and chip design are the two largest segments of the microelectronics value chain. While Europe is strengthening semiconductor fabrication and technology with considerable investments, e.g., in new fabs, chip design capabilities fall far short of the required capacities. The EU MicroElectronics Training, Industry and Skills (METIS) Report 2023 has shown that chip designers are the job profiles identified as the most difficult to find in the European microelectronics industry. European universities face many challenges hindering their ability to produce skilled graduates and contribute to the semiconductor ecosystem. While student interest in, e.g., AI is booming, we observe a decreasing interest in microelectronics. The main reasons for this are the high entry barriers for students, reinforced by the lack of chip design enablement in academia. Hence, there are ongoing initiatives in different European countries, on the EU level, and worldwide to strengthen chip design education and research. This focus session will bring together stakeholders of these initiatives from Europe and the USA to explore the critical challenges, opportunities, and potential strategies facing chip design enablement in European academic institutions. The session will be held in the panel format with active audience participation to guarantee inclusiveness and foster a broad view of the topic.

[paper] inductive nature of synapse potentiation

So-Yeon Kim, Heyi Zhang, Gonzalo Rivera-Sierra, Roberto Fenollosa, 

Jenifer Rubio-Magnieto, Juan Bisquert

Introduction to neuromorphic functions of memristors: 

The inductive nature of synapse potentiation

J. Appl. Phys. 21 March 2025; 137 (11): 111101

DOI: 10.1063/5.0257462

Abstract: Memristors are key elements for building synapses and neurons in advanced neuromorphic computation. Memristors are made with a wide range of material technologies, but they share some basic functionalities to reproduce biological functions such as synapse plasticity for dynamic information processing. Here, we explain the basic neuromorphic functions of memristors, and we show that the main memristor functionalities can be obtained with a combination of ordinary two-contact circuit elements: inductors, capacitors, resistors, and rectifiers. The measured IV characteristics of the circuit yield clockwise and counterclockwise loops, which are like those obtained from memristors. The inductor is responsible for the set of resistive switching, while the capacitor produces a reset cycle. By combining inductive and capacitive properties with gating variables represented by diodes, we can construct the full potentiation and depression responses of a synapse against applied trains of voltage pulses of different polarities. These results facilitate identifying the central dynamical characteristic required in the investigation of synaptic memristors.

Fig: Measurements performed on the capacitive–inductive circuit

including two rectifier diode elements.

Acknowledgments: The work was funded by the European Research Council (ERC) via Horizon Europe Advanced Grant, Grant Agreement No. 101097688 (“PeroSpiker”).

Data Availability: The data presented here can be accessed at https://doi.org/10.5281/zenodo.14184296 (Zenodo) under the license CC-BY-4.0 (Creative Commons Attribution-ShareAlike 4.0 International).

[C4P] Special Issue on Machine Learning for CAD

ACM Digital Library CALL FOR PAPERS — DEADLINE EXTENDED ACM Transactions on Design Automation of Electronic Systems Special Issue on Machine Learning for CAD Guest Editors Yibo Lin, Peking University Siddharth Garg, New York University Hussam Amrouch, Technical University of Munich (TUM) Advances in machine learning (ML) over the past half-dozen years have revolutionized the effectiveness of ML for a variety of applications. However, design processes present challenges that require parallel advances in ML and CAD as compared to traditional ML applications such as image classification. This seeks original submission on ML applications to the entire design flow of integrated circuits, from system-level design to manufacturing, from functional verification to testing, from design time to runtime, etc. Click here for the full Call for Papers and submission instructions. Important Dates Submissions deadline: March 5, 2025 — DEADLINE EXTENDED First-round review decisions: April 15, 2025 Deadline for revision submissions: May 15, 2025 Notification of final decisions: June 15, 2025 Tentative publication: Summer 2025 For questions and further information, please contact guest editors at: Yibo Lin, Peking University Siddharth Garg, New York University Hussam Amrouch, Technical University of Munich (TUM) Sign up for TODAES TOC alerts. https://todaes.acm.org You are subscribed with: wladek@grabinski.ch Unsubscribe The call-for-papers@hq.acm.org email address is not monitored. Please do not reply to it directly. Association for Computing Machinery 1601 Broadway, 10th Floor, New York, NY 10019 Connect with us:

[C4P] Speak at Open Source Summit Europe 2025

Present your work + ideas in Amsterdam, 25–27 August!

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