FreeCAD Beginner's Handbook

FreeCAD Beginner's Handbook by Aleksander Sadowski (Author)

ALSADO Independently Published

Publication Date: Dec. 26, 2025  (English, pp. 293)

ISBN-13: 979-8275865370

https://www.amazon.com/dp/B0G9HXYYGX

Learn 3D Design with FreeCAD Through Real-World Examples and Hands-On Projects

Discover the world of 3D design with FreeCAD, the free and open-source CAD software used by engineers, designers, and makers worldwide. This full-color, practical guide takes you step by step through a reliable modeling workflow, showing you how to create real-world products and inventions and even complete a complex project like designing a Mars Rover from scratch to solidify your knowledge.

Table of Contents

1. Working with 3D Shapes on Paper
2. Getting Started with Solid Modeling Theory
3. Quickstarting FreeCAD with your first 3D CAD Model
4. Creating Sketches using the Sketcher Workbench
5. Creating Parts using the Part Design Workbench
6. Creating Assemblies using the A2Plus Workbench
7. Preparing your FreeCAD Designs for 3D printing
8. Sharing your FreeCAD Designs in the Maker Community
9. Building the Mars Rover in FreeCAD from Scratch

About the author

Aleksander Sadowski is the founder of ALSADO, the world’s first company offering professional FreeCAD support in the industry. He is studying mechanical engineering at the Bonn-Rhein-Sieg University of Applied Sciences and has been actively involved in the FreeCAD community for many years. Aleksander is developing a workflow for product development in mechanical engineering, fully composed of open-source-software, including FreeCAD, LibreOffice, PrePoMax and OpenRadioss. Based on that he is developing an open-source-software to make collaboration in engineering teams more accessible to manufacturing start-ups and small to medium sized enterprises (SMEs).

In the past, Sadowski worked in product safety at the machine manufacturer GROB and at a company, that specializes in developing simulation software for defense applications. He has been collaborating with Altair, the association of German engineers (VDI) and the German space agency (DLR) to promote the use of open-source software in the industry, especially in mechanical engineering, automotive and aerospace. Aleksander Sadowski is the inventor of a safety screw, that he developed with the help of an open-source-workflow.

Through his books, Aleksander aims to reduce the beginner learning challenges and frustration by teaching a systematic process of working with FreeCAD consisting of most-used functions and a standard modeling workflow which he has refined through his years of experience of teaching FreeCAD in a productive and mission-critical environment. The books make this knowledge accessible to everyone, not just the companies.

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[Data] CMOS SKY130 Cryo Primitives

Akturk, Akin, Li, Anhang, Saligane, Mehdi, Riem, Joseph, Adam, Gina, Hoskins,

Brian D, Shrestha, Pragya

CMOS SKY130 Primitives measured at cryogenic temperatures

NIST, (2023: Part of CHIPS METIS Data Collection)

Version: 1.1. Revised: 2024-03-27

DOI: 10.18434/mds2-2997 (Accessed 2026-01-03)

Abstract: SKY130 is an open source complementary metal oxide semiconductor (CMOS) technology manufactured by Skywater Technology (SKY) in its facility in Bloomington, Minnesota. Since it is an open source technology, there are no legal restrictions on its characterization, unlike in typical foundry semiconductor technologies. To facilitate the development of cryogenic electronics, this data set includes measurements of devices manufactured in SKY130 at low temperatures.

Fig: NIST Cryo Circuit Module Description

Name	File Type	Size
2997_README_v4.txt	Plain text	4.46 kB
ETest Tile.zip	Compressed file archive	3.81 MB
MPW-5 Test Tile.zip	Compressed file archive	39.5 MB

[paper] Channel-last GAA nanosheet oxide FETs

Fabia F. Athena, Xiangjin Wu, Nathaniel S. Safron, Amy Siobhan McKeown-Green, Mauro Dossena, Jack C. Evans, Jonathan Hartanto, Yukio Cho, Donglai Zhong, Tara Pena, Paweł Czaja, Parivash Moradifar, Paul C. McIntyre, Mathieu Luisier, Yi Cui, Jennifer A. Dionne, Greg Pitner, Iuliana P. Radu, Eric Pop, Alberto Salleo, H.-S. Philip Wong

Channel-last gate-all-around nanosheet oxide semiconductor transistor

arXiv:2512.21330v1 [cond-mat.mtrl-sci] 24 Dec 2025

1. Department of Electrical Engineering, Stanford University, Stanford (US)
2. Corporate Research, Taiwan Semiconductor Manufacturing Company, Ltd., San Jose (US)
3. Department of Chemistry, Stanford University, Stanford (US)
4. Department of Information Technology and Electrical Engineering, ETH Zurich (CH)
5. Department of Material Science and Engineering, Stanford University, Stanford (US)
6. Department of Chemical Engineering, Stanford University, Stanford (US)
7. Applied Energy Division, SLAC National Accelerator Laboratory, Menlo Park (US)
8. Institute of Metallurgy and Materials Science, Polish Academy of Sciences (PL)
9. Corporate Research, Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)

Abstract: As we move beyond the era of transistor miniaturization, back-end-of-line compatible transistors that can be stacked monolithically in the third dimension promise improved performance for low-power electronics. In advanced transistor architectures, such as gate-all-around nanosheets, the conventional channel-first process involves depositing dielectrics directly onto the channel. Atomic layer deposition of gate dielectrics on back-end-of-line compatible channel materials, such as amorphous oxide semiconductors, can induce defects or cause structural modifications that degrade electrical performance. While post-deposition annealing can partially repair this damage, it often degrades other device metrics. We report a novel channel-last concept that prevents such damage. Channel-last gate-all-around self-aligned transistors with amorphous oxide-semiconductor channels exhibit high on-state current (> 1mAμm) and low subthreshold swing (minimum of 63mV/dec) without the need for post-deposition processing. This approach offers a general, scalable pathway for transistors with atomic layer deposited channel materials, enabling the future of low-power three-dimensional electronics.

Fig: Electrical performance of CL GAA FETs. (A) A SEM image of a representative device structure and (B) an AFM image of IWO deposited on a control sample show a uniform and smooth surface.  (C) IdVgs for a CL GAA FET with tch = 6nm measured at VDS = 0.05V and 1V. (D) IdVgs for a CL GAA FET with tch = 9 nm measured at VDS = 0.05V and 1V. Dual sweep shows very low hysteresis of about 0.038V at VDS = 0.05V.

Acknowledgment: Supported in part by SRC JUMP 2.0 PRISM and CHIMES Center, Stanford Differentiated Access Memory (DAM), SystemX Alliance, Stanford NMTRI, TSMC-Stanford Joint Development Project (P.C.M.). Part of this work was performed at Nano at Stanford (RRID SCR 026695). Authors acknowledge help and support for the AFM measurements from Christina Newcomb. Stanford authors thank MSS USA Corp. for high quality TEM sample preparation and examination and Dr. David Fried of Lam Research for providing access to Coventor SEMulator3D for process simulation. Use of the Stanford Synchrotron Radiation Lightsource at SLAC National Accelerator Laboratory is supported by the U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences under Contract No. DE-AC02-76SF00515. Y.C. acknowledges the support from the Japan Society for the Promotion of Science (JSPS) overseas research fellowship. J.A.D., A.M.G., and P.M. acknowledge the financial support from the U.S. Department of Energy Office of Science National Quantum Information Science Research Centers as part of the Q-NEXT center. Y.C. and F.F.A. would like to thank the support from the Stanford Energy Postdoctoral Fellowship and Precourt Institute for Energy.

[paper] Cryogenic CMOS Device Modeling

Zhidong Tang, Zewei Wang, Yumeng Yuan, Chang He, Xin Luo, Ao Guo, Renhe Chen, Yongqi Hu, Longfei Yang, Chengwei Cao, Linlin Liu, Liujiang Yu, Ganbing Shang, Yongfeng Cao, Shoumian Chen, Yuhang Zhao, Shaojian Hu, and Xufeng Kou

Generic Cryogenic CMOS Device Modeling and EDA-Compatible Platform 

for Reliable Cryogenic IC Design

IEEE JEDS, vol. 13, pp. 117-127 (2025)

DOI: 10.1109/JEDS.2025.3542589

1. ShanghaiTech University, Shanghai (CN)
2. University of Chinese Academy of Sciences, Beijing (CN)
3. Shanghai IC Research and Development Center, Shanghai (CN)
4. Huali Microelectronics Corporation (HLMC), Shanghai (CN)
5. School of Integrated Circuits, Tsinghua University, Beijing (CN)

Abstract: This paper outlines the establishment of a generic cryogenic CMOS database in which key electrical parameters and transfer characteristics of the MOSFETs are quantified as functions of device size, temperature, and frequency responses. Meanwhile, a comprehensive device statistical study is conducted to evaluate the influence of variation and mismatch effects at low temperatures. Furthermore, by incorporating the Cryo-CMOS compact model into the HLMC process design kit (PDK), the cryogenic 4Kb SRAM, 5-bit flash ADC and 8-bit current steering DAC are designed, and their performance is readily investigated and optimized on the EDA-compatible platform, hence laying a solid foundation for large-scale cryogenic IC design.

FIG: Schematic of the solid-state based quantum computer architecture 

with integrated quantum control system in a cryogenic environment.

Acknowledgments: This work was supported by the National Key R&D Program of China (2021YFA0715503, 2023YFB4404000), National Natural Science Foundation of China (92164104), the Strategic Priority Research Program of CAS (XDA18010000), Shanghai Rising-Star Program (21QA1406000) and the Open Fund of State Key Laboratory of Infrared Physics.

[paper] Efficient Long-Channel MOSFET Model

Ananda Sankar Chakraborty

Efficient Long-Channel MOSFET Model 

with SPICE-enabled Lambert W Function for Universal Application

Silicon (2025): 1-10; DOI 0.1007/s12633-025-03576-1

1 ETCE, Indian Institute of Engineering Science and Technology, Shibpur (IN)

Abstract: A novel, accurate charge-based MOSFET long-channel computational model is presented, which is portable and can be used across the electrical engineering domains ranging from sensing to power electronics, both under sub-threshold as well as super-threshold regime of MOSFET operation. The proposed physics-based model can be universally used to any long-channel MOS-transistor, as it does not depend on any empirical factor and features extremely good computational efficiency. The model uses a novel two-step charge linearization, resulting into accurate drain current and charge model – valid for both the subthreshold and super-threshold regime of long-channel MOSFET operation. Another salient feature of the proposed model is a novel SPICE-compatible numerical solution strategy for the principal branch of the Lambert W function (W0(x) for {x ∈ R | x ≥ 0}). The algorithm is faster than present industry standard implementations, computationally efficient, accurate with maximum percentage error≈10−14% and therefore may be incorporated in a SPICE engine for electrical design and optimization. The proposed computationally efficient long channel MOSFET model is validated against thorough TCAD simulations upto the fourth derivative and has been found to have fast convergence along with much higher degree of accuracy compared to existing MOSFET models.

FIG: Bulk-MOSFET structure: its current (I_DS) and conductance (g_DS) vs Drain Voltage (V_DS)

(Line: proposed model, symbol: TCAD)