[paper] ATMAD: Compact Modeling with Parameter Extraction

Yuhang Zhang, Qing Zhang, Yang Shen, Bingyi Ye, Xiaojin Li, Yabin Sun, Yanling Shi, Yong‑Fu Li

ATMAD: Agile Transistor Compact Modeling with Parameter Extraction 

Based on Automatic Differentiation

ACM 1084-4309/2026/04-ART103

DOI: 10.1145/3797484

1. School of Integrated Circuits, East China Normal University, Shanghai, China
2. Department of Micro‑Nano Electronics, Shanghai Jiao Tong University, Shanghai, China
3. East China Normal University, Shanghai, China
4. Shanghai Jiao Tong University, Shanghai, China

Abstract: Compact models of transistors are essential for simulating and optimizing circuits with the use of SPICE simulation tool. Parameter extraction, which is calibrating these models, is essential to ensure their alignment with measured or simulated data. However, conventional parameter extraction methods are generally iterative and experience-dependent, requiring significant time and effort from modeling engineers. Moreover, as semiconductor devices and compact models become increasingly advanced, the need for a tailored extraction process for each model has become increasingly inefficient. To address the above challenges, this work proposes an agile transistor compact modeling framework, ATMAD. The proposed framework takes a compact model file and a set of electrical characteristic data as inputs, producing a calibrated model with minimal human intervention. ATMAD automatically retrieves the equations in the compact model and converts them into computational flow graphs, thus supporting different compact models with a generalized process. A graph unlooping technique is proposed to support automatic differentiation for compact models with implicit functions (e.g., series resistance and surface potential solving). Based on the computational flow graph, ATMAD adopts automatic differentiation technique to achieve automatic and parallel optimization of model parameters. The proposed ATMAD framework is validated on commonly-used compact models in academia and industry, showing its effectiveness for compact modeling for both 𝐼𝑉 and 𝐶𝑉 characteristics.

Fig. The overall flow of ATMAD framework

Acknowledgements: This work is supported in part by the Shanghai Explorer Program under Grant No. 25TS1410300 and 24TS1400200 and in part by the National Natural Science Foundation of China under Grants No. 62304133 and 62350610271.

[paper] CrOx/TiOy Memristive Devices

Phu-Quan Pham1,2, Ngoc-Lam Le Pham3,4, Thuy-Anh Tran1,2, Van-Son Dang4, Quang Nguyen2,5, Ngoc Kim Pham1,2, Thuat Tran Nguyen3,4

On-Pinched Hysteresis in CrOx/TiOy-based Memristive Devices: Modeling and Analysis

Appl. Phys. Lett. 128, 153502 (2026)

DOI: 10.1063/5.0332014

1 Faculty of Materials Science and Technology, University of Science, Vietnam National University – Ho Chi Minh City, Ho Chi Minh City, 72754, Vietnam
2 Vietnam National University – Ho Chi Minh City, Ho Chi Minh City, 71309, Vietnam
3 Semiconductor and Advanced Materials Institute, Technology and Innovation Park, Vietnam National University – Hanoi, Hoa Lac, Hanoi, 13151, Vietnam.
4 Faculty of Physics, University of Science, Vietnam National University – Hanoi, 334 Nguyen Trai, Thanh Xuan, Hanoi, 11406, Vietnam
5 Department of Physics, International University, Vietnam National University – Ho Chi Minh City, Ho Chi Minh City, 71309, Vietnam

Abstract: Transition-metal oxide memristors are promising for neuromorphic computing, yet most SPICE models overlook material-specific effects such as oxygen stoichiometry and non-pinched hysteresis. Here, we systematically study CrOx/TiOy memristors fabricated under controlled oxygen concentrations (10%–50%) and propose an improved SPICE-compatible model. The devices exhibit oxygen-dependent resistive switching, retention, and pulse-driven plasticity, with optimal performance at 40% oxygen. Our model explicitly reproduces the non-pinched hysteresis observed in I–V curves, consistent with behaviors such as ion immigration, charge trapping, and remnant polarization, and achieves close agreement with experiments across multiple stoichiometries. Validation includes endurance, retention, and synaptic functions such as long-term potentiation/depression and spike-number/amplitude-dependent plasticity. Finally, the model is extended from single devices to a 4 × 4 crossbar array, demonstrating its scalability for artificial neural network simulations. These results emphasize the critical role of oxygen stoichiometry in CrOx/TiOy memristors and introduce a modeling framework that bridges experimental device physics with circuit-level neuromorphic applications.

Fig. a. Fabricated single cell memristor devic and b. 4×4 crossbar array

[paper] Thermal Management SiGe HBT in ICs

Boulgheb, Abdelaaziz

"Enhanced thermal management of SiGe HBT integrated circuits 

using the Peltier effect and DBC metal tracks"

Microelectronics Reliability 174 (2025): 115896

DOI: 10.1016/j.microrel.2025.115896

1 Department of Electronics, University of Sciences and Technology Houari Boumediene, Bab Ezzouar 16111, Algeria.
2 Hyperfrequencies and Semiconductors Laboratory, Department of Electronics, Faculty of Sciences and Technology, University of Frères Mentouri Constantine 1, PO Box 25017, Constantine, Algeria.

Abstract: Effective thermal management remains a major challenge for SiGe heterojunction bipolar transistor (HBT) integrated circuits, particularly in BiCMOS9MW 0.13µm technology. This study proposes a novel two-stage heat dissipation strategy that combines active thermoelectric cooling with passive DBC-based conduction an approach not previously explored in this context to address this issue. First, the Peltier effect is leveraged in combination with conventional plastic packaging to regulate circuit thermal performance. Second, Direct Bonded Copper (DBC) metal tracks are implemented to establish an efficient thermal pathway between the internal circuit and external heat sinks. Experimental results indicate that standard plastic packaging alone results in excessive heating (Tmax = 467 K). The incorporation of the Peltier effect significantly reduces the peak temperature to 380 K, while the addition of DBC tracks further enhances cooling, lowering the temperature to 340 K. Unlike traditional cooling solutions that rely solely on packaging or external heatsinks, our method enables localized, controllable heat extraction directly at the chip level, ensuring better thermal regulation and improved electrical performance. This dual approach not only mitigates self-heating but also leads to notable improvements in DC and RF performance. Specifically, the maximum current gain (βmax) increases from 1913 to 2183, and the transit frequency (ft) rises from 265 GHz to 285.6 GHz. These findings underscore the effectiveness of the combined Peltier-based cooling and DBC thermal management in enabling next-generation high-frequency applications.

Fig. a) SiGe HBT device structure simulated with COMSOL, showing the log of electron and hole concentrations. b) SEM cross-sectional view of the SiGe HBT.

Lin Fujian Optoelectronic Device Modeling Laboratory

Yangtze River Delta Integrated Circuit Industrial Application Technology Innovation Center

Jiangsu Jicui Integrated Circuit Application Technology Innovation Center

Lin Fujian Optoelectronic Device Modeling Laboratory

Optoelectronic Device Modeling Laboratory Services

• SPICE model development, characterization, and parameter extraction for silicon photonic waveguides and micro modulators and optical splitters/combiners
• Compact modeling, characterization, and parameter extraction for other advanced photonic devices
• GaN device characterization, EEHemt, ASM model and Angelov models
• InP‑HEMT device characterization, EEHemt model
• SiGe HBT device characterization, SPG/VBIC/HICUM model
• Characterization of micro‑/nano‑devices, internal/external parameter consistency studies, and high‑quality enhancement of existing models
• Ultra‑wideband SPICE models for electrical interconnects, packaging, and passive components
• Modeling of 1/f noise, noise parameters, avalanche effects, self‑heating, channel temperature, and related physical effects
• CNAS‑certified testing and final acceptance testing for major projects
• Other practical modeling services based on customer requirements

Laboratory Contact Information

联系人：小葛，18334212431，邮箱：gemy@jitric.cn

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定位：轻资产、高专业、全流程建模验证平台

合作模式：仪器有偿使用、可靠提参、技术赋能

[MEAD] Low-Power Analog IC Design

MEAD Education

June 22-26, 2026

Registration deadline: May 22, 2026

Payment deadline: June 12, 2026

MONDAY, June 22
8:30-12:00 am	MOS Transistor Modeling for Low-Voltage and Low-Power Circuit Design	Christian Enz
1:30-5:00 pm	Design of Low-Power Analog Circuits using the Inversion Coefficient	Christian Enz
TUESDAY, June 23
8:30-10:00 am	Noise Performance of Elementary Circuits	Boris Murmann
10:30-12:00 am	Noise Performance of Filters, Feedback & SC Circuits	Boris Murmann
1:30-3:00 pm	Opamp Topologies and Design: Single-Stage Circuits	Boris Murmann
3:30-5:00 pm	Opamp Topologies: Cascoded and Two-Stage Circuits	Boris Murmann

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