Apr 29, 2025

[paper] Avalanche Multiplication in SiGe HBTs

Zhang, Huaiyuan, Guofu Niu, Andries J. Scholten, and Marnix B. Willemsen
"Avalanche Multiplication Factor Modeling and Extraction at High Currents in SiGe HBTs"
IEEE Transactions on Electron Devices (2025)
DOI: 10.1109/TED.2025.3558114
1. Auburn University, Auburn, AL, USA
2. NXP, Eindhoven, The Netherlands

Abstract: A new compact model and an extraction method for avalanche multiplication factor (M-1) at high currents are proposed. At a fixed collector–base (CB) voltage (VCB), M-1 first decreases with increasing emitter current (IE) and then increases at higher currents when the Kirk effect occurs. Different forced-IE M-1 extraction techniques are evaluated, including a new compact modeling-based M-1 extraction technique that accurately captures the Early effect, the Kirk effect, and self-heating. The model is implemented in a development version of MEXTRAM and demonstrated experimentally to model both the current and bias dependence of M-1 and base current (IB). 

FIG: Simplified dc equivalent circuit of a transistor under forced IE,VCB 
and  fT(IE) meas/sim up to 150 mA at VCB = 1, 2, and 3 V (b)

Acknowledgment: The authors wish to acknowledge the support of the Compact Model Coalition (CMC).

Apr 26, 2025

Heading to San Francisco for ICMC 2025?

✈️ Heading to San Francisco for ICMC 2025?

The International Compact Modeling Conference (ICMC) is just 2 months away! Be sure to register and secure your room at the Clift Royal Sonesta. Book by May 26 to take advantage of a special discounted rate!

🔗 Register now: https://loom.ly/XmJUtI4
🔗 Reserve your room: https://loom.ly/zyzycVs


hashtag

Apr 25, 2025

[C4P] Micro-Nano 2025

International Conference on Micro- and Nanoelectronics, Nanotechnology and MEMS (MicroNano 2025)

https://2025.micro-nano.gr/



This annual Micro-Nano 2025 conference is organized by the Micro&Nano Scientific Society of Greece and aims to connect people from academia, research and industry, so as to stimulate discussions on the latest scientific achievements and to further promote micro- and nanotechnologies. The conference is held every time in a different city all around Greece, with the most recent one realized in Lemnos (2024). This year's Conference will be held on the island of Crete and is co-organized with the Technical University of Crete.

ABSTRACT SUBMISSION
  • Conference Dates: November 6-9, 2025
  • Submission Opens: will be announced
  • Abstract Submission Final Deadline: will be announced
  • Peer reviewing will follow immediately after submission.








Apr 24, 2025

[paper] Compact OTM-RRAM Characterization Platform

Max Uhlmann, Milosz Krysik, Jianan Wen, Max Frohberg, Andrea Baroni, Keerthi Dorai Swamy Reddy, 
Eduardo Pérez, Philip Ostrovskyy, Krzysztof Piotrowski, Corrado Carta, Christian Wenger, 
and Gerhard Kahmen
A Compact One-Transistor-Multiple-RRAM Characterization Platform
IEEE Transactions on Circuits and Systems I: Regular Papers (2025)
DOI: 10.1109/TCSI.2025.3555234
1. IHP GmbH Frankfurt (Oder) (D)
2. Faculty of Mathematics, Computer Science, Physics, Electrical Engineering and Information Technology, TU Brandenburg (D)
3. Institute of High-Frequency and Semiconductor System Technologies, TU Berlin (D)

Abstract: Emerging non-volatile memories (eNVMs) such as resistive random-access memory (RRAM) offer an alternative solution compared to standard CMOS technologies for implementation of in-memory computing (IMC) units used in artificial neural network (ANN) applications. Existing measurement equipment for device characterisation and programming of such eNVMs are usually bulky and expensive. In this work, we present a compact size characterization platform for RRAM devices, including a custom programming unit IC that occupies less than 1 mm2 of silicon area. Our platform is capable of testing one-transistor-one-RRAM (1T1R) as well as one-transistor-multiple-RRAM (1TNR) cells. Thus, to the best knowledge of the authors, this is the first demonstration of an integrated programming interface for 1TNR cells. The 1T2R IMC cells were fabricated in the IHP's 130 nm BiCMOS technology and, in combination with other parts of the platform, are able to provide more synaptic weight resolution for ANN model applications while simultaneously decreasing the energy consumption by 50%. The platform can generate programming voltage pulses with a 3.3 mV accuracy. Using the incremental step pulse with verify algorithm (ISPVA) we achieve 5 non-overlapping resistive states per 1T1R device. Based on those 1T1R base states we measure 15 resulting state combinations in the 1T2R cells.

FIG. The GDSII layout, schematic (a) and transmission electron microscopic (TEM) cross section image (b) of a 1T1R structure in IHP's 130 nm BiCMOS technology, with its material stack (c) and resitive switching mechanism principle (d).

Acknowledgement: This work was supported by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) under Project 434434223–SFB 1461

Apr 23, 2025

[mos-ak] [Announcement] MOS-AK INAOE Workshop, Puebla (MX), May 14-16, 2025


Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
MOS-AK INAOE Workshop
Puebla (MX), May 14-16, 2025

The semiconductor industry is crucial for Mexico's development, and it is the key for the future growth of the country economics. Producing advanced integrated circuits involves many steps, beginning with the idea for the circuits, technology, IC design and its simulation, layout generation, manufacturing and functional tests, among them. All of these stages require dedicated, specialized software programs, generally very expensive, which makes them onerous for the majority of academic institutions in the country. Recently, however, there has been an important effort in developing free open source tools for this purpose, and thus accessible to any educational institutions. These include open source tools spanning from the design to the fabrication of the circuits.  In these initial stages, having these tools available aims at fostering research and education in the field of prototyping IC design, without considering manufacturing in large quantities.

The mail goal of MOS-AK INAOE workshop is to expound on the available free open source tools for each IC development step in the design, simulation and manufacturing of integrated circuits, as well as presenting the options for the fabrication of ICs.

It is very important to train people, build the semi workforce with the basic knowledge needed to grow the semiconductor industry in Mexico. Professionals, including international researchers and experts from INAOE and other institutions, will give talks and courses to explain the tools, their potential uses, showing the engineering requirements and IC design applications.
 
The MOS-AK workshop program will be published online:

Space is limited, so we invite you to register at the following link:

-- R.Murphy and W.Grabinski 
-- on the behalf of the MOS-AK INAOE Organizing Committee

Enabling Compact Modeling R&D Exchange

WG230425

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