Jan 8, 2024

[paper] Polylogarithms in MOSFET Modeling

A. Ortiz-Conde and F. J. García-Sánchez
Recent Applications of Polylogarithms in MOSFET Modeling
2023 IEEE 33rd International Conference on Microelectronics
MIEL, Nis, Serbia, 2023, pp. 1-8
DOI: 10.1109/MIEL58498.2023.10315897

Department of Electronics and Circuits, Universidad Simón Bolívar, Caracas, Venezuela

Abstract: We present a review of recent uses of the special mathematical function known as the polylogarithm for MOSFET modeling applications. We first summarize some basic properties of polylogarithms, with a particular focus on those with negative exponential argument. After examining cases of the use of first order polylogarithms pertinent to electron device modeling, we explain the reasons that motivate the use of polylogarithms of diverse orders for formulating mono- and poly-crystalline succinct compact MOSFET models. We then analyze a particular representative example: the modeling of polysilicon MOSFETs using the polylogarithm. Recalling that polylogarithms may be used to faithfully represent Fermi-Dirac Integrals in general, and considering that they are analytically differentiable and integrable, we describe a full Fermi–Dirac Statistics-based version of the usually approximate Boltzmann Statistics-based MOSFET Surface Potential Equation (SPE).

TABLE: Some Features of Polylogarithms with Negative Exponential Argument



[paper] Compact Model of Graphene FETs

Nikolaos Mavredakis, Anibal Pacheco-Sanchez, Oihana Txoperena,
Elias Torres, and David Jiménez
A Scalable Compact Model for the Static Drain Current of Graphene FETs
IEEE TED, Vol. 71, No. 1, January 2024
DOI:  10.1109/TED.2023.3330713

1 Departament d’Enginyeria Electrònica, Escola d’Enginyeria, UAB, 08193 Bellaterra, Spain
2 Graphenea Semiconductor SLU, 20009 San Sebastián, Spain.

Abstract: The main target of this article is to propose for the first time a physics-based continuous and symmetric compact model that accurately captures I–V experimental dependencies induced by geometrical scaling effects for graphene field-effect transistor (GFET) technologies. Such a scalable model is an indispensable ingredient for the boost of large-scale GFET applications, as it has been already proved in solid industry-based CMOS technologies. Dependencies of the physical model parameters on channel dimensions are thoroughly investigated, and semi-empirical expressions are derived, which precisely characterize such behaviors for an industry-based GFET technology, as well as for others developed in the research laboratory. This work aims at the establishment of the first industry standard GFET compact model that can be integrated in circuit simulation tools and, hence, can contribute to the update of GFET technology from the research level to massive industry production.

Fig: Graphenea GFET schematic cross-section not drawn to scale. Graphene under metal contacts is not shown.The drain current has explicit derivation in respect to Qgr, where Qt and Qp(n) are the transport sheet and p(n)-type charges, respectively; Vc is the chemical potential, h is the reduced Planck constant, uf is the Fermi velocity, e is the electron charge, and k is a coefficient. Qt and, thus, ID can be calculated according to Vc polarity at source (Vcs) and drain (Vcd), respectively. Hence, at n-type region where Vcs, Vcd > 0 and Qp = 0

Acknowledgements: This work was supported in part by the European Union’s Horizon 2020 Research and Innovation Program GrapheneCore3 under Grant 881603; in part by the Ministerio de Ciencia, Innovación y Universidades under Grant RTI2018-097876-B-C21 (MCIU/AEI/ FEDER, UE), Grant FJC2020-046213-I, and Grant PID2021-127840NBI00 (MCIN/AEI/FEDER, UE); in part by the European Union Regional Development Fund within the Framework of the ERDF Operational Program of Catalonia 2014–2020 with the Support of the Department de Recerca i Universitat, with a grant of 50% of Total Cost Eligible; and in part by the GraphCAT Project under Grant 001-P-001702. 

Jan 5, 2024

ISHI-kai January 2024 event

2024年1月イベント「オープンソースPDK団体」勉強会国内外のオ
ープンソースPDKやEDAの状況について、キーマンに語っていただきます
With the recent rise in the semiconductor industry, the movement of open source PDK and EDA in Japan and overseas has become active. Therefore, in this study session, key people will talk about the status of open source PDK and EDA in Japan and overseas.

Schedule
Friday, January 26, 2024, 18:00-21:00 (Reception: 18:30)

Venue (onsite)
Google Shibuya Office
3-21-3 Shibuya, Shibuya-ku, Tokyo
Shibuya Stream Google reception meeting

Online Broadcast: 
Google Meet: https://meet.google.com/ksa-tjaw-ges

Participation Fee
free
Timetable
TimeSpeakerTitleLecture Outline
Until 18:30ISHI-kaireceptionThe entrance to the facility closes at this time, so if you are participating locally, please come by this time as much as possible.
18:00 ~ 18:30ISHI-kaiChat time-
18:30 ~ 19:15 (Lecture: 30min, Q&A: 15min)Takeshi Hamamoto
Minimal Fab Propulsion Organization Device Engineer 
minimal Fab open PDK1) What is a minimal fab
2) openPDK
3) Design Contest at Semicon 2023

19:15 ~ 20:00 (Lecture: 30min., Q&A: 15min.)Junichi Okamura
IEEE Senior Member 
OpenPDK and the World-
20:00 ~ 20:45 (Lecture: 30min., Q&A: 15min.)@noritsunaAbout the upcoming open source PDK shuttle(To be released at a later date)
21:00ISHI-kaiclosing

What is ISHI-kai?
The association was named ISHI-kai (Inter-linked Society on Homemade IC Kai). The name was conceived from the Society Community (Association) that handles open (democratized) ISHI = stone = Silicon = semiconductors (ASIC/LSI/IC) and connects various fields.

OpenMPW (Open Multi Project Wafer), which appeared as a forerunner, is a shuttle program created by Google investing in Efabless, and includes the tools necessary for making semiconductors (ASIC/LSI/IC) (EDA/PDK) to ISHI manufacturing in IC fabs). This is exactly the "openness of semiconductors (ASIC/LSI/IC) and EDA/PDK" of the open source movement (democratization of software) that started with GNU!

Therefore, this association was established as a user society community (association) that focuses not only on experts in semiconductors (ASIC/LSI/IC) in the past, but also on those who see the potential of the open source movement of semiconductors (ASIC/LSI/IC) in the future and those who want to create new semiconductors (ASIC/LSI/IC).

We/ISHI-kai will continue to work toward a world where semiconductors (ASIC/LSI/IC) and EDA/PDK can be used by everyone, just as OSs, compilers, libraries, apps, electronic boards, 3D CAD and 3D printers that we/ISHI-kaire only available to experts can now be used by everyone as open source software, open hardware, open modeling, etc.

As for the future activity plan, we/ISHI-kai have a policy of revolutionizing the semiconductor (ASIC/LSI/IC) field by involving people from other fields, and we/ISHI-kai will hold events such as hands-on seminars for ultra-beginners for other fields and in-depth study sessions for experts, form a team to challenge the OpenMPW shuttle and Chipathon from around the world, and Maker we/ISHI-kai would like to participate in events such as Faire, so thank you.

Precautions
As events move online, we/ISHI-kai ask participants to act in accordance with the spirit of the Code of Conduct. If you have any problems, please contact the organizer. If it is judged that there is no improvement in the request even if there is no abuse such as vandalism or malicious intent, we/ISHI-kai may respond on a case-by-case basis. 
https://www.contributor-covenant.org/ja/version/2/0/code_of_conduct/

Acknowledgements
Thanks to the kindness of Google for providing a real/onsite venue.

Jan 3, 2024

VLSID 2024 Conference


PULP Platform @pulp_platform (5h)
Cheers to 2024! The 37th International Conference on VLSI Design will start in Kolkata on Monday. @LucaBenini will give a banquet talk titled "Open Platform for the Embodied AI Era" at 7:10 PM (IST) on January 9. Check out the conference website for tutorials and schedule: https://vlsid.org

In the present era of automation and connected things, VLSI technology armed with AI and Quantum could be pivotal in changing the VLSI landscape starting from manufacturing to devices to design. To elaborate on this paradigm shift, the theme 2024 VLSI Design conference is aptly chosen to be “VLSI meets AI and Quantum for Cyber Physical Systems”.

Over a span of five-days of VLSID2024, the summit will feed brains and nurture minds with state-of-the-art exhibitors, presentations, panel discussions, innovation forums, and tutorials by established technologists.

[paper] MEMS pressure sensors

Xiangguang Han, Mimi Huang, Zutang Wu, Yi Gao, Yong Xia, Ping Yang, Shu Fan, Xuhao Lu, Xiaokai Yang, Lin Liang, Wenbi Su, Lu Wang, Zeyu Cui, Yihe Zhao, Zhikang Li, Libo Zhao
and Zhuangde Jiang
Advances in high-performance MEMS pressure sensors: design, fabrication, and packaging.
Microsyst Nanoeng 9, 156 (2023) 
DOI:10.1038/s41378-023-00620-1

1 State Key Laboratory for Manufacturing Systems Engineering, Xi’an Jiaotong University, Xi’an 710049, China
2 International Joint Laboratory for Micro/Nano Manufacturing and Measurement Technologies, Xi’an Jiaotong University, Xi’an 710049, China.
3 School of Mechanical Engineering, Xi’an Jiaotong University, Xi’an 710049, China.
4 Northwest Institute of Nuclear Technology, Xi’an 710024, China


Abstract: Pressure sensors play a vital role in aerospace, automotive, medical, and consumer electronics. Although microelectromechanical system (MEMS)-based pressure sensors have been widely used for decades, new trends in pressure sensors, including higher sensitivity, higher accuracy, better multifunctionality, smaller chip size, and smaller package size, have recently emerged. The demand for performance upgradation has led to breakthroughs in sensor materials, design, fabrication, and packaging methods, which have emerged frequently in recent decades. This paper reviews common new trends in MEMS pressure sensors, including minute differential pressure sensors (MDPSs), resonant pressure sensors (RPSs), integrated pressure sensors, miniaturized pressure chips, and leadless pressure sensors. To realize an extremely sensitive MDPS with broad application potential, including in medical ventilators and fire residual pressure monitors, the “beam-membrane-island” sensor design exhibits the best performance of 66 μV/V/kPa with a natural frequency of 11.3 kHz. In high-accuracy applications, silicon and quartz RPS are analyzed, and both materials show ±0.01%FS accuracy with respect to varying temperature coefficient of frequency (TCF) control methods. To improve MEMS sensor integration, different integrated “pressure + x” sensor designs and fabrication methods are compared. In this realm, the intercoupling effect still requires further investigation. Typical fabrication methods for microsized pressure sensor chips are also reviewed. To date, the chip thickness size can be controlled to be <0.1 mm, which is advantageous for implant sensors. Furthermore, a leadless pressure sensor was analyzed, offering an extremely small package size and harsh environmental compatibility. This review is structured as follows. The background of pressure sensors is first presented. Then, an in-depth introduction to MEMS pressure sensors based on different application scenarios is provided. Additionally, their respective characteristics and significant advancements are analyzed and summarized. Finally, development trends of MEMS pressure sensors in different fields are analyzed.

Fig: High-sensitivity MDPS, on-chip amplified MDPS, and resonant MDPS.

Acknowledgements: This study was supported in part by the National Key Research and Development Program of China (2021YFB3203200) and the Natural Scienc Foundation of Shaanxi (2022JQ-554).