Apr 25, 2022

[paper] DC, LF noise and TID mechanisms in 16nm FinFETs

Stefano Bonaldoab, Teng Maab, Serena Mattiazzobc, Andrea Baschirottode, Christian Enzf, Daniel M.Fleetwoodg, Alessandro Paccagnellaab, Simone Gerardinab
DC response, low-frequency noise, and TID-induced mechanisms in 16-nm FinFETs for high-energy physics experiments
J. NIMA Section A; available online 18 April 2022, 166727
DOI: j.nima.2022.166727
     
a University of Padova (I)
b INFN Padova (I)
c University of Padova (I)
d INFN Milano (I)
e University of Milano Bicocca (I)
f ICLab, EPFL, Lausanne (CH)
g Vanderbilt University, Nashville (USA)

Abstract: Total-ionizing-dose (TID) mechanisms are evaluated in 16nm Si bulk FinFETs at doses up to 1 Grad (SiO2) for applications in high-energy physics experiments. The TID effects are evaluated through DC and low-frequency noise measurements by varying irradiation bias conditions, transistor channel lengths, and fin/finger layouts. The TID response of nFinFETs irradiated under positive gate bias at ultrahigh doses shows a rebound of threshold voltage with significant increase in the 1/f noise amplitude. The degradation is related to the generation of border and interface traps at the upper corners of STI oxides and at the gate oxide/channel interfaces. In contrast, pFinFETs have the worst degradation due to positive charge trapping in STI oxides, which severely degrades the device transconductance and total drain current, while negligible effects are visible in the threshold voltage and 1/f noise. The TID sensitivity depends strongly on the transistor layout. Short-channel devices have the best TID tolerance thanks to the influence of halo implantation, while pFinFETs designed with low number of fins have the worst degradation because of high densities of positive charge in the surrounding thick STI oxides. As a guideline for IC design, short-channel transistors with more than 4-fins may be preferred in order to facilitate circuit qualification.
Fig: Low-frequency noise measured at |Vds|=50mV and |Vgs|=0.85V at room temperature for pFinFET with Nfin=2 and L=16 nm, irradiated up to 1Grad (SiO2) in the ON condition

Acknowledgment: This work has been carried out within the FinFET16v2 experiment funded by the National Institute for Nuclear Physics - INFN, Italy.




Apr 12, 2022

[paper] Roadmapping of Nanoelectronics for the New Electronics Industry

Paolo Gargini1,Francis Balestra2, and Yoshihiro Hayashi3
Roadmapping of Nanoelectronics for the New Electronics Industry
Appl. Sci. 2022, 12(1), 308
DOI: 10.3390/app12010308
Received: 4 November 2021 / Revised: 17 December 2021 
Accepted: 20 December 2021 / Published: 29 December 2021
Academic Editor: Gerard Ghibaudo; This article belongs to the Special Issue Advances in Microelectronic Materials, Processes and Devices
   
1IEEE IRDS, (US)
2 CNRS, Grenoble INP (F)
3 Keio University, Tokyo (J)


Abstract: This paper is dedicated to a review of the international effort to map the future of nanoelectronics from materials to systems for the new electronics industry. The following sections are highlighted: the Roadmap structure with the international teams, the methodology and historical evolution, the various eras of scaling, the new ecosystems and computer industry, the evolving supply chain, the development of SoC and SiP, the advent of the Internet of Everything and the 5G communications, the dramatic increase of data centers, the power challenge, the technology fusion, heterogeneous and system integration, the emerging technologies, devices and computing architectures, and the main challenges for future applications.
FIG: 40 Years of Microprocessor Trend Data

[webinar] Prof. Benjamin Iniguez' IEEE EDS DL on “2D Semiconductor FET Modeling”



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Apr 11, 2022

[paper] Noise Degradation and Recovery in Gamma-irradiated SOI nMOSFET

S.Amorab, V.Kilchytskaa, F.Tounsia, N.Andréa, M.Machhoutb, L.A.Francisa, D.Flandrea
Characteristics of noise degradation and recovery in gamma-irradiated SOI nMOSFET
with in-situ thermal annealing
Solid-State Electronics; 108300; online 7 April 2022, 
DOI: 10.1016/j.sse.2022.108300
   
a SMALL, ICTEAM Institute, Université catholique de Louvain (B)
b Faculté des Sciences de Université de Monastir (TN)


Abstract: This paper demonstrates a procedure for complete in-situ recovery of on-membrane CMOS devices from total ionizing dose (TID) defects induced by gamma radiation. Several annealing steps were applied using an integrated micro-heater with a maximum temperature of 365°C. The electrical characteristics of the on-membrane nMOSFET are recorded prior and during irradiation (up to 348 krad (Si)), as well as after each step of the in-situ thermal annealing. High-resolution current sampling measurements reveal the presence of oxide defects after irradiation, with a clear dominant single-trap signature in the random telegraph noise (RTN) traces. Drain current over time measurements are used for the trap identification and further for the defects' parameters extraction. The power spectral density (PSD) curves confirm a clear dominance of the RTN behavior in the low-frequency noise. A radiation-induced oxide trap is detected at 5.4 nm from the Si-SiO2 interface, with an energy of 0.086 eV from the Fermi level in the bandgap. After annealing, the RTN behavior vanishes with a further important reduction of flicker noise. Low-frequency noise measurements of the transistor confirmed the neutralization of oxide defects after annealing. The electro-thermal annealing of the nMOSFET allows a total recovery of its original characteristics after being severely degraded by radiation-induced defects.

Fig: Device under test : (a) cross-section schematic, (b) microscopic front view
showing the membrane and other embedded elements





Apr 8, 2022

#Soitec s’allie à #STM, #GF et au #CEA-Leti pour faire avancer les puces #FD-SOI



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