Call for Papers - IEEE Special Issue of T-ED

Call for Papers - IEEE Special Issue of T-ED on #Semi #Device #Modeling for #Circuit and #System Design Submission Deadline: 30 April 2023 Learn More & Submit: https://t.co/GdNbNufQxH #ElectronDevicesSociety #ElectronDevices #semiconductor #emergingsem…https://t.co/iGSHSjXaxn

— Wladek Grabinski (@wladek60) Jan 19, 2023

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from Twitter https://twitter.com/wladek60

January 19, 2023 at 04:32PM
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#NIST and #Google to Create New Supply of #Chips for Researchers and Startups

#NIST and #Google to Create New Supply of #Chips for Researchers and #Semi Tech Startups https://t.co/hP6Ek2bmVK https://t.co/pdrUROnzzF

— Wladek Grabinski (@wladek60) Jan 19, 2023

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from Twitter https://twitter.com/wladek60

January 19, 2023 at 01:35PM
via IFTTT

IEEE EDS MQ at NIT Silchar Silchar, Assam (IN)

IEEE EDS Mini-Colloquium 

on Micro/Nanoelectronics, Devices, Circuits and Systems, 

29-31 Jan 2023 (Hybrid Mode)

DATES	LOCATION	HOST	REGISTER
Date: 29 Jan 2023 Time:10:00AM to 06:00PM  (UTC+05:30)  Add Event to Calendar  iCal  Google Calendar	National Institute of Technology Silchar Dept of ECE, NIT Silchar Silchar, Assam India 788010 Building: ECE/CSE Building	National Inst of Technology - Silchar, ED15 Kolkata Section Chapter NANO42 Co-sponsored by Dr. Trupti R. Lenka	Starts Dec.1, 2022 Ends Jan.28,2023 No Admission Charge Register NOW

Agenda with following contribution Distinguished Lecturers: 

• Anil Kottantharayil (anilkg@ieee.org)
• Gananath Dash (gndash@ieee.org)
• Ajit Kumar Panda (akpanda62@hotmail.com)
• Manoj Saxena (msaxena@ieee.org)
• Brajesh Kumar Kaushik (bkkaushik23@gmail.com)
• Samar Saha (samar@ieee.org)
• Hiroshi Iwai (h.iwai@ieee.org)
• Taiichi Otsuji (taiichi.otsuji.e8@tohoku.ac.jp)
• Pei-Wen Li (pwli@nycu.edu.tw)
• Zhou Xing (EXZHOU@ntu.edu.sg)
• Albert Chin (albert_achin@hotmail.com)
• Mansun Chan (mchan@ust.hk)
• Chao-Sung LAI (cslai@mail.cgu.edu.tw)
• Wladek Grabinski, MOS-AK, EU (wladek@grabinski.ch)

Register NOW

Neural networks and machine learning approach for compact modeling

[NN] Wang, Qiuwei, Mao Ye, Yao Li, Xiaoxiao Zheng, Jiaji He, Jun Du, and Yiqiang Zhao. "MOSFET modeling of 0.18 μm CMOS technology at 4.2 K using BP neural network." Microelectronics Journal (2023): 105678. DOI: 10.1016/j.sse.2022.108580

Highlights

• The cryogenic characterization of SMIC CMOS technology at 4.2K is presented.
• An optimization model VCCS is proposed to calibrate the cryogenic characteristics.
• BP neural network is, for the first time, used in MOSFET modeling.
• The cryo-model can be applied to SPICE simulator and assist in cryo-CMOS circuit design and simulation.

Fig: The structure of graph-based compact model of FinFET. The model receives the input features such as voltages, geometries, etc. as a vector and predicts the drain current (Ids) and its derivatives as output features.

[ML] Gaidhane, Amol D., Ziyao Yang, and Yu Cao. "Graph-based Compact Modeling (GCM) of CMOS transistors for efficient parameter extraction: A machine learning approach." Solid-State Electronics (2023): 108580.

Highlights

• Developed a Graph-based compact model for FinFET.
• Model implemented in Verilog-A for SPICE simulation.
• Requires less number of model parameters and is computationally efficient than BSIM

[mos-ak] [Prennouncement] 7th Sino MOS-AK Workshop in Nanjing (CN)

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

7th Sino MOS-AK Workshop in Nanjing (CN)

scheduled for August 11-13, 2023 (online/onsite)

Preannouncement and Call for Papers

Together with local host, as well as all the Extended MOS-AK TPC Committee, would like to invite you to the 7th Sino MOS-AK Workshop in Nanjing (CN) which will be organized as the online/onsite event on August 11-13, 2023 providing an opportunity to meet the internation modeling experts, engineers and researchers. A training course related to SiC topic (device modeling, packaging models, circuits, modules and final application) is planned for the first MOS-AK day, following by two days of the MOS-AK compact/SPICE modeling and its Verilog-A discussions. 

Upcoming, subsequent 7th Sino MOS-AK Workshop in Nanjing (CN) aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors, in particular using Free open source PDKs.

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source (FOSS) TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, Organic TFT, CMOS and SOI-based memory
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
• Technology R&D, DFY, DFT and reliability/aging IC designs
• Foundry/Fabless Interface Strategies (eg: using Free open source PDKs)

Important Dates:

• Call for Papers - Jan 2023
• 2nd Announcement - April 2023
• Final Workshop Program - July 2023
• 7th Sino MOS-AK Workshop -  Aug. 11-13, 2023 (online/onsite)