Jun 29, 2021

#Garage #Semi #Fab Gets Reactive-Ion Etching Upgrade https://t.co/Idbflx3oZN https://t.co/mw0q6ZdCmw

#Garage #Semi #Fab Gets Reactive-Ion Etching Upgrade https://t.co/Idbflx3oZN https://t.co/mw0q6ZdCmw
— Wladek Grabinski (@wladek60) Jun 29, 2021

from Twitter https://twitter.com/wladek60

June 29, 2021 at 02:53PM
via IFTTT

[paper] Nano Device Simulator

Zlatan Stanojevic , Member, IEEE, Chen-Ming Tsai, Georg Strof, Ferdinand Mitterbauer, Oskar Baumgartner, Member, IEEE, Christian Kernstock, and Markus Karner, Member, IEEE

Nano Device Simulator - A Practical Subband-BTE Solver for Path-Finding and DTCO

in IEEE TED, Open Access, June 2021

DOI: 10.1109/TED.2021.3079884.

Global TCAD Solutions GmbH, 1010 Vienna

Abstract: We present an in-depth discussion on the subband Boltzmann transport (SBTE) methodology, its evolution, and its application to the simulation of nanoscale MOSFETs. The evolution of the method is presented from the point of view of developing a commercial general purpose SBTE solver, the GTS nano device simulator (NDS). We show a wide range of applications SBTE is suited for, including state-of-the-art nonplanar and well-established planar technologies. It is demonstrated how SBTE can be employed both as a path-finding tool and a fundamental component in a DTCO-flow.

Fig: NDS simulation of a device generated using level-set topography simulation; left: level-set generated FinFET with complex warped surfaces, typical of topography simulation; the analytical doping is shown; middle: the SBTE domain is cut out of the device and meshed using an extruded grid, and mixed with the mesh of the rest of the device; cuts are then extracted from the SBTE domain and remeshed; right: electron drift velocity in the FinFET, DD versus SBTE; the SBTE result clearly shows the velocity overshoot effect not seen in the DD solution.

Acknowledgment: The authors would like to thank Dr. Edward Chen for many fruitful discussions and the continued valuable feedback.

Jun 28, 2021

South #Korea targets 2028 for first #6G network [Report https://t.co/bKmu4qQ6Ln] #semi https://t.co/MNuL4ssbw5

South #Korea targets 2028 for first #6G network [Report https://t.co/bKmu4qQ6Ln] #semi https://t.co/MNuL4ssbw5
— Wladek Grabinski (@wladek60) Jun 28, 2021

from Twitter https://twitter.com/wladek60

June 28, 2021 at 02:49PM
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[paper] RTN and BTI statistical compact modeling

G.Pedreira^a, J.Martin-Martinez^a, P.Saraza-Canflanca^b, R.Castro Lopez^b, R.Rodriguez^a, E.Roca^b, F.V.Fernandez^b, M.Nafria^a

Unified RTN and BTI statistical compact modeling from a defect-centric perspective

Solid-State Electronics

Available online 25 June 2021, 108112

In Press, Journal Pre-proof

DOI: 10.1016/j.sse.2021.108112

a Universitat Autònoma de Barcelona (UAB), Electronic Engineering Department, REDEC group. Barcelona, Spain
b Instituto de Microelectrónica de Sevilla, IMSE-CNM, CSIC and Universidad de Sevilla, Spain

Abstract: In nowadays, deeply scaled CMOS technologies, time-dependent variability effects have become important concerns for analog and digital circuit design. Transistor parameter shifts caused by Bias Temperature Instability and Random Telegraph Noise phenomena can lead to deviations of the circuit performance or even to its fatal failure. In this scenario extensive and accurate device characterization under several test conditions has become an unavoidable step towards trustworthy implementing the stochastic reliability models. In this paper, the statistical distributions of threshold voltage shifts in nanometric CMOS transistors will be studied at near threshold, nominal and accelerated aging conditions. Statistical modelling of RTN and BTI combined effects covering the full voltage range is presented.

The results of this work suppose a complete modelling approach of BTI and RTN that can be applied in a wide range of voltages for reliability predictions.

Program 2021: Symposium on Schottky Barrier MOS Devices

The symposium goal is to combine the activities of an enthusiastic group of Schottky barrier researchers worldwide. The topics cover all important aspects of potential applications, simulation and modeling, processing and implementation for CMOS/SOI technologies, Quantum technologies and approaches for neuromorphic applications. The content will be beneficial for anyone who needs to learn the opportunities and challenges of this technology since the first introduction by Walter Schottky in the 1938s. New aspects and future proposals to make the Schottky barrier into the main stream are welcome.

Program 2021

Wed 30.06.2021 (Virtual)

13:00-13:05	Opening IEEE DL
13:05-14:00	IEEE Distinguished Lecture: Tunneling Graphene FET Gana Nath Dash, Sambalpur University (IN) Abstract: During the last few decades, aggressive scaling in Si MOSFET (Metal Oxide Semiconductor Field Effect Transistor) architecture has given rise to several short channel effects, which in turn has set a performance limit on the device owing to constraint in Si technology. The emergence of graphene at this juncture with a host of exotic and favorable electronic properties, generated new hopes for the FET industry. While the graphene based analogue FET witnessed some advantages, the digital counterpart showed a dismal performance, primarily due to the zero bandgap of graphene (poor ON/OFF ratio). For a way out, an alternative architecture based on the quantum tunneling process is augmented with the graphene FET resulting in the new device named TGFET.

14:00-14:05	Opening SSBMOS
14:05-14:35	Germanium nanosheet and nanowire transistor technologies for beyond CMOS applications Walter M. Weber, Raphael Böckle, Lukas Wind, Kilian Eysin, Daniele Nazzari, Tatli Ezgi, Oliver Solfronk, Alois Lugstein and Masiar Sistani, Institute of Solid State Electronics, TU Vienna (A) Abstract: The ultimate downscaling limits of conventional field effect transistors calls for alternative computational methods that provide perspectives towards the enhancement of computational complexity, circuit performance and energy efficiency. In this sense germanium nano-transistors offer both an approachable access to quantum confinement effects and promising electronic transport properties that distinctly are compatible with modern CMOS fabrication flows. We will discuss the applicability of different germanium active regions and gating architectures towards the realization of computational electronics with added functionality. On top of exploring different realizations of reconfigurable transistors with programmable polarity we will discuss further functionality enhancement by enabling operability within the negative differential resistance regime at room temperature. Prospective implications at the circuit level will be discussed.
14:40-15:10	Evolving contact-controlled thin-film transistors Radu Sporea, University of Surrey (UK) Abstract: TFT designs that comprise multiple gates and rectifying source contacts can be designed to produce linear transconductance and act as robust amplifiers and signal converters. This talk outlines device design and opportunities in emerging edge processing applications.
15:10-15:50	COFFEE BREAK
15:50-16:20	Compact Modelling of Dually-Gated Reconfigurable Field-Effect Transistors Christian Römer, Ghader Darbandy, Mike Schwarz, Jens Trommer, André Heinzig, Thomas Mikolajick, Walter M. Weber, Benjamín Iñíguez** and Alexander Kloes* NanoP, THM (DE), namLAB, TU Dresden (DE), TU Vienna (A), DEEEA, URV (ES) Abstract:** This work presents a closed-form and physics-based DC compact model, which is applicable on dually-gated reconfigurable field-effect transistors (RFETs). The presented compact model is focused on the charge-carrier injection at the device’s source and drain side Schottky barriers, which can be separated into field emission and thermionic emission current contributions. This work explains the basic equations which are used to calculate the current contributions and shows calculated device characteristics compared to measurements.
16:25-16:55	The Schottky barrier transistor in all its forms Laurie Calvet, John P. Snyder, Mike Schwarz** C2N, University Paris (FR),* JCap, LLC (USA), *NanoP, THM (DE) Abstract:** The Schottky barrier (SB) transistor, where the source and drain of a conventional planar MOSFET are replaced with metallic contacts, was first explored in the 1960s. Since then, many variations on this structure have been explored in the literature including: different semiconductors materials such as other non-organic semiconductors and nano-structures such as carbon nanotubes and nanowires. In this talk we review some of the changes in the electronic transport that are observed as the geometry and materials of the SB transistors are changed.