Principles, Applications, And The Future Of #Piezoelectric #MEMS https://t.co/1tVZd6d9xI#semi pic.twitter.com/vgcNu4WGpt
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May 26, 2021 at 10:43AM
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May 26, 2021
Principles, Applications, And The Future Of #Piezoelectric #MEMS https://t.co/1tVZd6d9xI #semi https://t.co/vgcNu4WGpt
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May 26, 2021 at 10:43AM
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May 25, 2021
Global #200mm #Fab Capacity on Pace to Record Growth
Global #200mm #Fab Capacity on Pace to Record Growth to Meet Surging Demand and Address #Chip Shortage [SEMI Reports] https://t.co/U6URwtE98e #semi pic.twitter.com/auVdEwdRh3
— Wladek Grabinski (@wladek60) May 25, 2021
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May 25, 2021 at 08:28PM
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#US #chip stimulus could unlock $150 billion, create 10 #fabs
#US #chip stimulus could unlock $150 billion, create 10 #fabs [May 25, 2021 // By Peter Clarke] https://t.co/xqP16Mel2Z #semi pic.twitter.com/KbfISHIH0W
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[papers] Aging and Device Reliability Compact Modeling
IEEE International Reliability Physics Symposium
(IRPS 2021)
[1] N. Chatterjee, J. Ortega, I. Meric, P. Xiao and I. Tsameret, "Machine Learning On Transistor Aging Data: Test Time Reduction and Modeling for Novel Devices," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-9, doi: 10.1109/IRPS46558.2021.9405188.
Abstract: Accurately modeling the I-V characteristics and current degradation for transistors is central to predicting circuit end-of-life behavior. In this work, we propose a machine learning model to accurately model current degradation at various stress conditions and extend that to make nominal use-bias predictions. The model can be extended to track and predict any parametric change. We show an excellent agreement of the model with experimental results. Furthermore, we use a deep neural network to model the I-V characteristics of aged transistors over a wide drain and gate playback bias range and show an excellent agreement with experimental results. We show that the model is reliably able to interpolate and extrapolate demonstrating that it learns the underlying functional form of the data.
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405188&isnumber=9405088
[2] P. B. Vyas et al., "Reliability-Conscious MOSFET Compact Modeling with Focus on the Defect-Screening Effect of Hot-Carrier Injection," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-4, doi: 10.1109/IRPS46558.2021.9405197.
Abstract: Accurate prediction of device aging plays a vital role in the circuit design of advanced-node CMOS technologies. In particular, hot-carrier induced aging is so complicated that its modeling is often significantly simplified, with focus limited to digital circuits. We present here a novel reliability-aware compact modeling method that can accurately capture the full post-stress I-V characteristics of the MOSFET, taking into account the impact of drain depletion region on induced defects.
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405197&isnumber=9405088
[3] Z. Wu et al., "Physics-based device aging modelling framework for accurate circuit reliability assessment," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-6, doi: 10.1109/IRPS46558.2021.9405106.
Abstract: An analytical device aging modelling framework, ranging from microscopic degradation physics up to the aged I-V characteristics, is demonstrated. We first expand our reliability oriented I-V compact model, now including temperature and body-bias effects; second, we propose an analytical solution for channel carrier profiling which-compared to our previous work-circumvents the need of TCAD aid; third, through Poisson's equation, we convert the extracted carrier density profile into channel lateral and oxide electric fields; fourth, we represent the device as an equivalent ballistic MOSFETs chain to enable channel “slicing” and propagate local degradation into the aged I-V characteristics, without requiring computationally-intensive self-consistent calculations. The local degradation in each channel “slice” is calculated with physics-based reliability models (2-state NMP, SVE/MVE). The demonstrated aging modelling framework is verified against TCAD and validated across a broad range of VG/VD/T stress conditions in a scaled finFET technology.
URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405106&isnumber=9405088
Circuit Design and Simulation Marathon using eSIM
Indian Institute of Technology, Bombay
To know more about the Circuit Design and Simulation Marathon, please visit https://hackathon.fossee.in/esim/
Important dates:
>> Registration: 21 May 2021 - 15 June 2021
>> Marathon Launch : 17 June 2021
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