Jan 4, 2021

[paper] Compact Modeling of Carbon Nanotube FETs

A Compact and Robust Technique for the Modeling and Parameter Extraction 
of Carbon Nanotube Field Effect Transistors
Laura Falaschetti1, Davide Mencarelli1, Nicola Pelagalli1, Paolo Crippa1, Giorgio Biagetti1,
Claudio Turchetti1,George Deligeorgis2, and Luca Pierantoni1
Electronics 2020, 9(12), 2199; 
DOI: 10.3390/electronics9122199

1 Department of Information Engineering, Marche Polytechnic University, 60131 Ancona, Italy
2 Microelectronics Research Group (MRG/IESL), FORTH, Greece


Abstract: Carbon nanotubes field-effect transistors (CNTFETs) have been recently studied with great interest due to the intriguing properties of the material that, in turn, lead to remarkable properties of the charge transport of the device channel. Downstream of the full-wave simulations, the construction of equivalent device models becomes the basic step for the advanced design of high-performance CNTFET-based nanoelectronics circuits and systems. In this contribution, we introduce a strategy for deriving a compact model for a CNTFET that is based on the full-wave simulation of the 3D geometry by using the finite element method, followed by the derivation of a compact circuit model and extraction of equivalent parameters. We show examples of CNTFET simulations and extract from them the fitting parameters of the model. The aim is to achieve a fully functional description in Verilog-A language and create a model library for the SPICE-like simulator environment, in order to be used by IC designers.
Figure 2. 3D structure of CNTFET. Reprinted, with permission, from [I and II]

Aknowlwgement: This research was supported by the European Project “NANO components for electronic SMART wireless circuits and systems (NANOSMART)”, H2020—ICT-07-2018-RIA, n. 825430.

References:
[I] Deng, J.; Wong, H.P. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including non-idealities and Its Application—Part I: Model of the Intrinsic Channel Region. IEEE Trans. Electron Devices 2007, 54, 3186–3194
[II] Deng, J.; Wong, H.P. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including non-idealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking. IEEE Trans. Electron Devices 2007, 54, 3195–3205 




Tentative Technical Program Schedule of the Webinar Series

The Tentative Technical Program Schedule of the Webinar Series 
jointly organized by 
The National Academy of Sciences India - Delhi Chapter 
and Science Foundation & MoE-IIC-DDUC Chapter,
Deen Dayal Upadhyaya College (University of Delhi) 
under the aegis of DBT Star College Program

Kindly see the attachment: for attending one or more Webinars, you are requested to register yourself with the ZOOM Webinar Link https://us02web.zoom.us/webinar/register/WN_iXRnhVc9SxWrSOD9CWTITA and also join the TELEGRAM group (https://t.me/joinchat/UEnJfvW8kcHf_Jmo) for receiving all updates about the Webinar Series. The Exact title of the Talks (which are missing as of now) and the time shall be shared by January 25, 2021 in the telegram group.

Kindly forward this message and attachment to your students and colleagues so that they can also register and join the telegram group.
  • E-Certificate will be provided like earlier programs.
  • Zoom Platform will be used for conducting Online Programs
Coordinator:
Dr. Manoj Saxena | डॉ मनोज  सक्सेना 
Program Coordinator - MoE IIC DDUC Chapter
Associate Professor | सह - आचार्य
Department of Electronics | इलेक्ट्रॉनिक्स विभाग
Deen Dayal Upadhyaya College | दीन दयाल उपाध्याय कॉलेज
University of Delhi | दिल्ली विश्वविद्यालय
Dwarka Sector-3, New Delhi-110078 | द्वारका क्षेत्र -, नई दिल्ली -११००७८
India | भारत

What Might the “#1nm #Node” Look Like? by Tom Dillinger; Semiwiki https://t.co/aP6kX33h0W #semi https://t.co/noo3g0hMSZ



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January 04, 2021 at 11:31AM
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Dec 24, 2020

[paper] IGBT Compact Modeling

Compact Modeling of IGBT Charging/Discharging for Accurate Switching Prediction
Y. Miyaoku1, A. Tone1, K. Matsuura1, M. Miura-Mattausch1 (Fellow, IEEE),
H. J. Mattausch1 (Senior Member, IEEE), and D. Ikoma2
IEEE J-EDS, vol. 8, pp. 1373-1380, 2020
doi: 10.1109/JEDS.2020.3008919
1 Graduate School of Advanced Sciences of Matter, Hiroshima University, Higashi-Hiroshima 739-8527, Japan
2 Sensor and Semiconductor Development, Denso Corporation, Aichi 448-8661, Japan


ABSTRACT The trench-type IGBT is one of the major devices developed for very high-voltage applications, and has been widely used for the motor control of EVs as well as for power-supply systems. In the reported investigation, the accurate prediction of the power dissipation of IGBT circuits has been analyzed. The main focus is given on the carrier dynamics within the IGBTs during the switching-off phase. It is demonstrated that discharging and charging at the IGBT’s gate-bottom-overlap region, where electron discharging is followed by hole charging, has an important influence on the switching performance. In particular, the comparison of long-base and short-base IGBTs reveals, that a quicker formation of the neutral region within the resistive base region, as occurring in the long-base IGBT, leads to lower gatebottom-overlap capacitance, thus realizing faster electron discharging and hole charging of this overlap region.
FIG: IGBT structures with nMOSFET + pnp BJT part (a. and b.) and nMOSFET-only structure (c.). The X–Y line is through the middle of the bottom-gate oxide and the A–B line is directly underneath the bottom-gate oxide.

Received 14 May 2020; revised 2 July 2020; accepted 8 July 2020. Date of publication 13 July 2020; date of current version 8 December 2020. The review of this article was arranged by Editor M. Mierzwinski. Digital Object Identifier 10.1109/JEDS.2020.3008919