#GNU #Health #Embedded #OpenSource Health Platform Works on Raspberry Pi 3/4, and soon Olimex SBC's https://t.co/mIXu3NfQPy https://t.co/I0tkTqXijs

#GNU #Health #Embedded #OpenSource Health Platform Works on Raspberry Pi 3/4, and soon Olimex SBC's https://t.co/mIXu3NfQPy pic.twitter.com/I0tkTqXijs

— Wladek Grabinski (@wladek60) June 16, 2020

from Twitter https://twitter.com/wladek60

June 16, 2020 at 04:46PM
via IFTTT

[paper] TFT Compact Modeling

Arun Dev Dhar Dwivedi, Sushil Kumar Jain, Rajeev Dhar Dwivedi and Shubham Dadhich

Numerical Simulation and Compact Modeling 

of Thin Film Transistors for Future Flexible Electronics

Submitted: July 4th 2019Reviewed: October 28th 2019Published: June 10th 2020

DOI: 10.5772/intechopen.90301

Abstract: In this chapter, we present a finite element method (FEM)-based numerical device simulation of low-voltage DNTT-based organic thin film transistor (OTFT) by considering field-dependent mobility model and double-peak Gaussian density of states model. Device simulation model is able to reproduce output characteristics in linear and saturation region and transfer characteristics below and above threshold region. We also demonstrate an approach for compact modeling and compact model parameter extraction of organic thin film transistors (OTFTs) using universal organic TFT (UOTFT) model by comparing the compact modeling results with the experimental results. Results obtained from technology computer-aided design (TCAD) simulation and compact modeling are compared and contrasted with experimental results. Further we present simulations of voltage transfer characteristic (VTC) plot of polymer P-channel thin film transistor (PTFT)-based inverter to assess the compact model against simple logic circuit simulation using SmartSpice and Gateway.

Fig.: Schematic cross-sectional diagram of organic TFTs 

along with the chemical structure of SAM and organic semiconductor.

Acknowledgments: The authors are thankful to SERB, DST, Government of India, for the financial support under Early Career Research Award (ECRA) for Project No. ECR/2017/000179.

#Intel’s #10nm Node: Past, Present, and Future [EETimes] https://t.co/P3Fi3xUogJ #paper https://t.co/QoFX5z22br

#Intel’s #10nm Node: Past, Present, and Future [EETimes] https://t.co/P3Fi3xUogJ #paper pic.twitter.com/QoFX5z22br

— Wladek Grabinski (@wladek60) June 16, 2020

from Twitter https://twitter.com/wladek60

June 16, 2020 at 02:31PM
via IFTTT

[slides] (Ultra-) Wide-Bandgap Devices

(Ultra-) Wide-Bandgap Devices: Reshaping the Power Electronics Landscape

Presenter Dr. Yuhao Zhang, Assistant Professor,
Center for Power Electronics Systems, Virginia Tech

IEEE EDS SCV-SF Seminar 

Friday, June 12, 2020 at 12PM – 1PM PDT

Abstract: Power electronics is the application of solid-state electronics for the control and processing of electrical energy. It is used ubiquitously in consumer electronics, electric vehicles, data centers, renewable energy systems, and smart grid. The power semiconductor device, as the cornerstone technology in power electronics, is key to improving the efficiency, cost and form factor of power electronic systems.  Recently, the power electronics landscape has been significantly reshaped with the production and application of power devices based on wide-bandgap (WBG) semiconductors, such as gallium nitride (GaN) and silicon carbide (SiC). Besides advancing the performance of traditional power systems, WBG devices have also enabled many emerging applications that are beyond the realm of silicon (Si) as well as changed the manufacturing paradigm of power electronics. On the horizon is the power devices based on ultra-wide-bandgap (UWBG) materials, which promises superior performance over GaN and SiC and is at the relatively early stage of research development.  This talk will provide a comprehensive overview of major WBG and UWBG power device technologies, spanning materials, devices, reliability and applications. Some research projects in the PI’s group in collaboration with industry will also be introduced.

FIG: WBG Semiconductor: Superior Power Semiconductor Over Si

The seminar presentation is now available on our IEEE EDS SCV-SF webpage:
http://site.ieee.org/scv-eds/files/2020/06/SCV_SF_EDS_Yuhao_Zhang_excerpt.pdf

More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page. Subscribe or Invite your friends to sign up for our mailing list and get to hear about exciting electron-device relevant talks. We, EDS SCV-SF, promise no spam and try to minimize email. You can (un)subscribe easily.

[paper] Future of Ultra-Low Power SOTB CMOS

Nobuyuki Sugii¹, Shiro Kamohara², Makoto Ikeda³

The Future of Ultra-Low Power SOTB CMOS Technology and Applications

NANO-CHIPS 2030. The Frontiers Collection. Springer, Cham

DOI: 10.1007/978-3-030-18338-7_6

1.Hitachi, Ltd.Tokyo, Japan
2.Renesas Electronics Corp.Tokyo, Japan
3.The University of Tokyo, Japan

Abstract: Ultra-low power technology has drawn much attention recently as the number of connecting (Internet-of-Things) devices rapidly increases. The silicon-on-thin-buried oxide (SOTB) technology is a CMOS device technology that uses fully depleted silicon-on-insulator (FDSOI) transistors with a thin buried oxide layer enabling enhanced back-bias controllability and that can be monolithically integrated with the conventional bulk CMOS circuits. It can significantly reduce both the operation and the standby powers by taking advantage of low-voltage operation and back-biasing, respectively. In this chapter, advantages of the SOTB technology in terms of ultra-low power, circuits design and chip implementation examples including ultra-low power micro-controllers operating with harvested power, reconfigurable logic circuits, analog circuits, are reviewed, and a future perspective is shown.

Fig.: Schematic cross section of SOTB transistors. Hybrid bulk transistors are shown. SOTB  transistors are used in low-voltage (< ~1.5 V) logic and analog circuits including SRAMs. Bulk  transistors are used in peripheral, ESD-protection, high-voltage analog and power circuits, on-chip,  flash memory, and reuse of legacy circuits

Acknowledgements: The part of the work, especially on developing the SOTB technology by the Low-power Electronics Association and Project (LEAP), is supported by the Ministry of Economy, Trade and Industry (METI) and the New Energy and Industrial Technology Development Organization (NEDO). Part of the chip fabrication by the universities is done under a support of VLSI Design and Education Center (VDEC) in collaboration with Renesas Electronics Corporation, Cadence Corporation, Synopsys Corporation and Mentor Graphics Corporation.