FOSS CAD research is in the spotlight

The conference paper "FOSS as an efficient tool for extraction of MOSFET compact model parameters" reached 20 reads at the researchgate.net

FOSS as an efficient tool for extraction of MOSFET compact model parameters

D. Tomaszewski, G. Głuszko, M. Brinson, V. Kuznetsov and W. Grabinski

MIXDES 2016, Lodz, pp. 68-73.

doi: 10.1109/MIXDES.2016.7529702

Abstract—A GNU Octave – based application for device-level compact model evaluation and parameter extraction has been developed. The applications main features are as follows: experimental I-V data importing, generating input data for different circuit simulation programs, running the simulation program to calculate I-V characteristics of the specified models, calculating model misfit and its sensitivity to selected parameter variation, and the comparison of experimental and simulated characteristics. Measured I-V data stored by different measurement systems are accepted. Circuit simulations may be done with Ngspice, Qucs and LTSpiceIV. Selected aspects of the application are presented and discussed. 

Ken Shirriff Takes Us Inside the IC, For Fun https://t.co/QScTdhgFXV #papers

Ken Shirriff Takes Us Inside the IC, For Fun https://t.co/QScTdhgFXV #papers

— Wladek Grabinski (@wladek60) December 27, 2016

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December 27, 2016 at 09:24PM
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J-EDS Comes of Age https://t.co/4HNl9cQhzh #papers

J-EDS Comes of Age https://t.co/4HNl9cQhzh #papers

— Wladek Grabinski (@wladek60) December 27, 2016

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December 27, 2016 at 01:07PM
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Special Issue of Solid-State Electronics, dedicated to EUROSOI-ULIS 2016 https://t.co/fFD9GehZEP #papers #feedly

Special Issue of Solid-State Electronics, dedicated to EUROSOI-ULIS 2016 https://t.co/fFD9GehZEP #papers #feedly

— Wladek Grabinski (@wladek60) December 25, 2016

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December 25, 2016 at 09:14PM
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[paper] Analysis and Compact Modeling of Negative Capacitance Transistor

Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current
and Negative Output Differential Resistance
Part II: Model Validation

Girish Pahwa, Student Member, IEEE, Tapas Dutta, Member, IEEE, Amit Agarwal,
Sourabh Khandelwal, Member, IEEE, Sayeef Salahuddin, SM IEEE,
Chenming Hu, IEEE Fellow, and Yogesh Singh Chauhan, SM IEEE 

in IEEE Transactions on Electron Devices, vol. 63, no. 12, pp. 4986-4992, Dec. 2016

doi: 10.1109/TED.2016.2614436

Abstract: In this paper, we show a validation of our compact model for negative capacitance FET (NCFET) presented in Part I. The model is thoroughly validated with the TCAD simulations with respect to ferroelectric thickness scaling and temperature effects. Interestingly, we find that an NCFET with PZT ferroelectric of a large thickness provides a negative output differential resistance in addition to an expected high ON current and a sub-60 mV/decade subthreshold swing. The model is also tested for the Gummel symmetry and its transient capabilities are highlighted through a ring oscillator circuit simulation.

[read more at IEEE Xplore]