Showing posts with label SBD. Show all posts
Showing posts with label SBD. Show all posts

Sep 29, 2026

[paper] TCAD Modeling of SB Diode

Pedro Paulo Pessoa Oliveira1,2, Andreas Mai1,3, Norbert Herfurth1, 
and Davies William de Lima Monteiro2
TCAD Modeling of Schottky-Diode in an open-source SiGe BiCMOS technology
In 2026 40th Symposium on Microelectronics Technology and Devices 
SBMicro, pp. 1-4. IEEE, 2026
DOI: 10.1109/SBMicro70495.2026.11684441

1. IHP, Frankfurt (Oder), Germany
2. Department of Electrical Engineering, UFMG - Belo Horizonte-MG, Brazil
3. University of Applied Sciences Wildau, Germany

Abstract: Accurate simulation of Schottky barrier diodes (SBDs) is challenging because standard idealized models fail to capture non-ideal interface physics, such as Fermi-level pinning and image-force lowering. This paper presents an enhanced Technology Computer-Aided Design (TCAD) methodology to model an SBD from the IHP SG13G2 130-nm open-source SiGe BiCMOS technology. To overcome limitations of conventional simulations that often rely on oversimplified assumptions and empirical fitting, this work explicitly incorporates interface en- ergy states into the simulation, specifically modeling the fun- damental pinning mechanisms driven by Metal-Induced Gap States (MIGS). By calibrating the TiSi2/Si interface using the theoretical slope parameter, a value of 0.503 V was determined for the zero-bias barrier height. The resulting physics-based model captures the true rectifying nature of the contact and accurately reproduces the electrical characteristics targeted by the empirical model, achieving a nominal forward voltage drop of 0.39 V and a realistic reverse leakage current of 29.3 nA at -2.5 V. Ultimately, this paper shows the innovation and education gain of open- source foundry data by showcasing an open innovation path for a targeted near-industry device development flow.
FIG: a.) Energy band diagram of the Schottky diode at V=0V. Thecoordinate x = 0 corresponds to the TiSi2/n-Si Schottky interface. The inset displays the 2D device schematic, with the solid black line indicating the multi-segment cut-path used to extract the energy levels across the anode, n-buried layer and n-well RT to cathode contact. b.) Comparison of the simulated DC current-voltage (IV) characteristics between the proposed TCAD model and the standard SPICE macromodel.

Acknowledgment: The authors thank IHP for the open-source PDK and the collaborative research. They also thank Universidade Federal de Minas Gerais (UFMG) and the Brazilian Microelectronics Society (SBMicro) for supporting this work. Finally, gratitude is extended to S. Srivastava and B. Sake for their valuable guidance.