[paper] Scalable Open-Source Multi-Project SoC Architecture

Uriel Jaramillo-Toral, Susana Ortega-Cisneros, Héctor Emmanuel Muñoz-Zapata, 

Iraam Antonio López-Salas 

Silicluster v2: A Scalable Open-Source Multi-Project SoC Architecture 

in Sky130 CMOS Enabling High-Density Modular Integration

in IEEE Access, vol. 14, pp. 82876-82889, 2026

doi: 10.1109/ACCESS.2026.3698053. 

* CINVESTAV, Guadalajara, Jalisco, Mexico

* Tecnológico Nacional de México, ITA, Aguascalientes, Mexico

Abstract: The increasing availability of open-source electronic design automation (EDA) tools and publicly accessible process design kits (PDKs) has expanded access to integrated circuit (IC) development; however, scalable system-level integration frameworks capable of supporting heterogeneous digital, analog, and mixed-signal systems remain limited. This paper presents Silicluster Version 2 (Silicluster v2), a hierarchical and scalable multi-project system-on-chip (SoC) architecture implemented in 130 nm complementary metal-oxide-semiconductor (CMOS) technology using a fully open-source register-transfer-level (RTL) to Graphic Data System II (GDSII) layout design flow. The proposed architecture enables the structured integration of up to 256 independent digital, analog, and mixed-signal modules within a single chip while preserving modular isolation, reusability, and routing efficiency. In contrast to its previous digital-focused implementation, Silicluster v2 incorporates infrastructure supporting transistor-level analog layout, parasitic-aware mixed-domain co-simulation using Simulation Program with Integrated Circuit Emphasis (SPICE), and integration of synthesized standard-cell netlists alongside custom transistor-level blocks. A hierarchical multiplexed interconnection scheme and centralized clock-distribution strategy mitigate fanout, congestion, and timing-closure challenges inherent to high-density modular integration. The complete system is validated through design rule checking (DRC), layout-versus-schematic (LVS) verification, parasitic extraction, and static timing analysis (STA) at 10 MHz, targeting 1.8 V digital operation and 3.3 V analog operation. The results demonstrate the feasibility of constructing complex heterogeneous integrated circuits using exclusively open-source methodologies, establishing Silicluster v2 as a validated reference architecture for collaborative silicon integration and scalable multi-project chip development.

Fig: Graphical representation of the Silicluster v2 integration process within Caravel. The original user area is replaced by the Silicluster v2 wrapper, enabling high-density modular integration and resulting in a complete MPW-ready SoC while preserving the RISC-V subsystem and padframe infrastructure.

Acknowledgment: The authors gratefully recognize ChipFoundry for enabling the fabrication of Silicluster v2 through the MPW Program. Their support made the physical realization of the proposed architecture possible. They also acknowledge Toyohashi University of Technology (TUT) for its early-stage mentorship in analog design methodologies and the Centro de Investigación y de Estudios Avanzados del IPN, Unidad Guadalajara (CINVESTAV), for providing the academic environment and institutional framework that supported the development of this project.