Francesco Gagliardi, Paolo Bruschi, Massimo Piotto, Soumaya Sakouhi, Michele Dei
Ultralow-Voltage NMOS-Only Voltage Reference with High-Frequency PSR Optimization
via Decoupling Pseudo-Resistor
IEEE ACCESS • Vol. 14, 2026
DOI: 10.1109/ACCESS.2026.3707314
Dipartimento di Ingegneria dell’Informazione, University of Pisa, 56122 Pisa (I)
Abstract: The design of integrated circuits operating at minimal supply voltage and power levels is a key requirement for energy-harvested smart sensing devices. This paper presents a novel NMOS-only 4-transistor voltage reference (VR) that exploits a self-cascode technique with high-frequency power-supply rejection (PSR) optimization through a decoupling pseudo-resistor. Post-layout simulations of a 0.18‑μm CMOS design show low-supply compliance and robustness to process-voltage-temperature variations. The output voltage is 177 mV with line sensitivity of 54 ppm/V in the 0.4–1.8 V supply range, PSR lower than –40 dB down to 0.28 V supply, simulated current consumption of 223 pA, and a mean temperature coefficient of 24.44 ppm/°C from –20 °C to 80 °C. The compact area footprint is 115.2 μm². The results indicate potential for stable low-voltage and low-power voltage reference implementations.
Fig: Small-signal equivalent circuits of (a) the 2T-VR and (b) the 3T-VR. The high-frequency path highlighted in (b) causes a limitation of the 3T-VR topology discussed at the end of this section.
Acknowledgements: This work was supported in part by the National Recovery and Resilience Plan (NRRP) of Italian Ministry of University and Research (MUR) funded by the European Union (EU) NextGenerationEU with the Project HeMoWear under Grant 0004610/2022, and in part by the European Innovation Council (EIC) through the Project Green valorization of CO2 and Nitrogen compounds for making fertilizers (CONFETI) under Grant 101115182. The associate editor coordinating the review of this manuscript and approving it for publication was Poki Chen.
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