[SIA] appreciate President Biden's strong support for swift enactment

We [SIA] appreciate President Biden's strong support for swift enactment of competitiveness legislation including $52 billion to incentivize #semi research, design, and manufacturing in the United States. https://t.co/CGxBdnq14s

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[mos-ak] [online publications] Q1 2022 MOS-AK Panel

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

Q1 2022 MOS-AK Panel

Online Publications

The Extended MOS-AK Committee, has organized a very first MOS-AK Panel to discuss the FOSS EDA tools for the compact/SPICE modeling and its Verilog-A standardization and implementation. The Q1 2022 MOS-AK Panel was organized as the virtual/online event on Feb.25, 2022, with practive participation of leading FOSS EDA developers representing GnuCap, ngspice, Qucs, Xyce teams.

Online Publications:

There are MOS-AK technical presentations covering selected aspects of the compact/SPICE modeling and its Verilog-A standardization; see submitted slide presentations online at corresponding link:

https://www.mos-ak.org/panel_Q1_2022/

The MOS-AK Panelists have also contributed to FOSS EDA/Verilog-A SWOT Analysis, with selected points listed in the table below. The FOSS EDA community has a number of challenges to address, in particular, securing financial support for FOSS EDA tools developments, especially for those outside of the corporate/academic environment, is of primary concern.

The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses around the globe thru the Next 2022 Year, including:

• Spring MOS-AK Workshop (online) Mar/Apr 2020
• 4th MOS-AK/LAEDC Workshop, Cancun (MX) July 2022
  
• 6th Sino MOS-AK Workshop (CN), Aug. 2022
• 20th MOS-AK/ESSDERC/ESSCIRC, Milano Sept.19, 2022
• 3rd MOS-AK/India Conference, Hyderabad (IN) Postponed 2022
• 15th US MOS-AK Workshop, Silicon Valley (US) Dec. 2022
• in timeframe of IEDM and Q4 CMC Meetings

W.Grabinski on the behalf of International MOS-AK Committee

WG02032022

Table: FOSS EDA/Verilog-A SWOT Analysis

Strengths	Weaknesses
High number of potential users both in terms of EDA companies/vendors and designers High number of potential contributors once a tool as been established as "gold standard"	At least a bit financial support will be needed in the long-run
Opportunities	Challenges
A "gold standard" Verilog-A compiler, i.e. sth. Like gcc, g++ or gfortran is currently not available for Verilog-A Improve the usefulness of open-source tools dramatically Enabler for research around the world  Further improving the Verilog-A standard and enabling new modeling technologies in the long-term	Securing financial support for FOSS developments, especially for those outside of the corporate/academic environment Teamwork, between projects

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[paper] Circuit-Based Compact Model of Electron Spin Qubit

Mattia Borgarino

Circuit-Based Compact Model of Electron Spin Qubit

Special Issue Recent Advances in Silicon-Based RFIC Design;

Electronics 2022, 11(4), 526; 

DOI: 10.3390/electronics11040526

   
University of Modena and Reggio Emilia, Modena (IT)

Abstract: Today, an electron spin qubit on silicon appears to be a very promising physical platform for the fabrication of future quantum microprocessors. Thousands of these qubits should be packed together into one single silicon die in order to break the quantum supremacy barrier. Microelectronics engineers are currently leveraging on the current CMOS technology to design the manipulation and read-out electronics as cryogenic integrated circuits. Several of these circuits are RFICs, as VCO, LNA, and mixers. Therefore, the availability of a qubit CAD model plays a central role in the proper design of these cryogenic RFICs. The present paper reports on a circuit-based compact model of an electron spin qubit for CAD applications. The proposed model is described and tested, and the limitations faced are highlighted and discussed.

FIG: Compact model of the electron spin qubit.

Funding: This research received no external funding.

[paper] SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology

Tianshi Liu¹, Hua Zhang¹, Sundar Babu Isukapati², Emran Ashik³, Adam J. Morgan², Bongmook Lee³, Woongje Sung², Ayman Fayed¹, Marvin H. White¹, and Anant K. Agarwal¹

SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology

IEEE Journal of the Electron Devices Society, vol. 10, pp. 129-138, 2022, 

DOI: 10.1109/JEDS.2022.315036

   
1 Department of Electrical & Computer Engineering, The Ohio State University, Columbus, OH 43210, USA
2 College of Nanoscale Science and Engineering, State University of New York Polytechnic Institute, Albany, NY 12309, USA
3 Department of Electrical & Computer Engineering, North Carolina State University, Raleigh, NC 27695, USA

Abstract: Silicon carbide (SiC) power integrated circuit (IC) technology allows monolithic integration of 600 V lateral SiC power MOSFETs and low-voltage SiC CMOS devices. It enables application-specific SiC ICs with high power output and work under harsh (high-temperature and radioactive) environments compared to Si power ICs. This work presents the device characteristics, SPICE modeling, and SiC CMOS circuit demonstrations of the first two lots of the proposed SiC power IC technology. Level 3 SPICE models are created for the high-voltage lateral power MOSFETs and low-voltage CMOS devices. SiC ICs, such as the SiC CMOS inverter and ring oscillator, have been designed, packaged, and characterized. Proper operations of the circuits are demonstrated. The effects of the trapped interface charges on the characteristics of SiC MOSFETs and SiC ICs are also discussed.

FIG: Cross-sectional view of the SiC MOSFETs (lot2)

Acknowledgment The authors would like to thank the team at Analog Devices (ADI), Hillview facility for the fabrication of devices and Advanced Research Projects Agency-Energy (ARPA-E). The authors also thank D. Xing for providing the customized gate driver for the dynamic characterizations of the circuits

[paper] Multi-Segment TFT Compact Model for THz Applications

Xueqing Liu¹,Trond Ytterdal² and Michael Shur^1,3

Multi-Segment TFT Compact Model for THz Applications

Nanomaterials 2022, 12(5), 765; 

DOI: 10.3390/nano12050765

  
1 RPI, Troy, NY 12180, USA
2 Norwegian University of Science and Technology, Trondheim, Norway
3 Electronics of the Future, Inc., USA

Abstract: We present an update of the Rensselaer Polytechnic Institute (RPI) thin-film transistor (TFT) compact model. The updated model implemented in Simulation Program with Integrated Circuit Emphasis (SPICE) accounts for the gate voltage-dependent channel layer thickness, enables the accurate description of the direct current (DC) characteristics, and uses channel segmentation to allow for terahertz (THz) frequency simulations. The model introduces two subthreshold ideality factors to describe the control of the gate voltage on the channel layer and its effect on the drain-to-source current and the channel capacitance. The calculated field distribution in the channel is used to evaluate the channel segment parameters including the segment impedance, kinetic inductance, and gate-to-segment capacitances. Our approach reproduces the conventional RPI TFT model at low frequencies, fits the measured current–voltage characteristics with sufficient accuracy, and extends the RPI TFT model applications into the THz frequency range. Our calculations show that a single TFT or complementary TFTs could efficiently detect the sub-terahertz and terahertz radiation.

FIG: (a) quivalent circuit of the multi-segment SPICE model for TFT and
(b) equivalent circuit for each segment including leakage components

Acknowledgements: The work was supported by Office of Naval Research (N000141712976, Project Monitor Paul Maki).