[mos-ak] [2nd Announcement and C4P] 18th MOS-AK ESSDERC/ESSCIRC Workshop (virtual/online) Sept.6, 2021

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

18th MOS-AK ESSDERC/ESSCIRC Workshop

Grenoble, Sept. 6, 2021

2nd Announcement and C4P

Together with local host CEA-Let and STM, lead sponsor ASCENT+, as well as all the Extended MOS-AK TPC Committee, would like to invite you to the 18th MOS-AK ESSDERC/ESSCIRC Workshop Compact/SPICE Modeling Workshop which will be organized as the virtual/online event on Sept. 6, 2021, preceding the ESSDERC/ESSCIRC Conference.

Planned virtual 18th MOS-AK ESSDERC/ESSCIRC Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source (FOSS) TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, Organic TFT, CMOS and SOI-based memory
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
• Technology R&D, DFY, DFT and reliability/aging IC designs
• Foundry/Fabless Interface Strategies

Speakers' tentative list includes the following names (in alphabetic order):

• Hussam Amrouch; KTI (DE)
• Sheikh Aamir Ahsanl; NIT Srinagar (IN)
• Mohamed Aouad, CEA-Leti (FR)
• Natalia Seoane Iglesias; USC University (ES)
• Muhammad Hussain; UCB (US)
• Sergey Kokin; MEPHI (RU)
• Luisa Petti; Free University of Bozen-Bolzano (IT)
• Paul Roseingrave; Tyndall (IE)
• Olivier Rozeau; CEA-Leti (FR)
• Valentin O. Turin; Orel State University (RU)

Online Abstract Submission to be open in July 2021

(any related enquiries can be sent to abstract@mos-ak.org)

Online Workshop Registration to be in August 2021

(any related enquiries can be sent to register@mos-ak.org)

Important Dates: 

• Call for Papers - April 2021
  
• 2nd Announcement - June 2021
• Final Workshop Program - Aug 2021
• MOS-AK Workshop - Sept.6, 2021
• as Virtual Educational Event at ESSDERC/ESSCIRC

W.Grabinski for Extended MOS-AK Committee

WG300621

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#Garage #Semi #Fab Gets Reactive-Ion Etching Upgrade https://t.co/Idbflx3oZN https://t.co/mw0q6ZdCmw

#Garage #Semi #Fab Gets Reactive-Ion Etching Upgrade https://t.co/Idbflx3oZN https://t.co/mw0q6ZdCmw

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June 29, 2021 at 02:53PM
via IFTTT

[paper] Nano Device Simulator

Zlatan Stanojevic , Member, IEEE, Chen-Ming Tsai, Georg Strof, Ferdinand Mitterbauer, Oskar Baumgartner, Member, IEEE, Christian Kernstock, and Markus Karner, Member, IEEE

Nano Device Simulator - A Practical Subband-BTE Solver for Path-Finding and DTCO

in IEEE TED, Open Access, June 2021

DOI: 10.1109/TED.2021.3079884.

Global TCAD Solutions GmbH, 1010 Vienna

Abstract: We present an in-depth discussion on the subband Boltzmann transport (SBTE) methodology, its evolution, and its application to the simulation of nanoscale MOSFETs. The evolution of the method is presented from the point of view of developing a commercial general purpose SBTE solver, the GTS nano device simulator (NDS). We show a wide range of applications SBTE is suited for, including state-of-the-art nonplanar and well-established planar technologies. It is demonstrated how SBTE can be employed both as a path-finding tool and a fundamental component in a DTCO-flow. 

Fig: NDS simulation of a device generated using level-set topography simulation; left: level-set generated FinFET with complex warped surfaces, typical of topography simulation; the analytical doping is shown; middle: the SBTE domain is cut out of the device and meshed using an extruded grid, and mixed with the mesh of the rest of the device; cuts are then extracted from the SBTE domain and remeshed; right: electron drift velocity in the FinFET, DD versus SBTE; the SBTE result clearly shows the velocity overshoot effect not seen in the DD solution.

Acknowledgment: The authors would like to thank Dr. Edward Chen for many fruitful discussions and the continued valuable feedback.

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South #Korea targets 2028 for first #6G network [Report https://t.co/bKmu4qQ6Ln] #semi https://t.co/MNuL4ssbw5

— Wladek Grabinski (@wladek60) Jun 28, 2021

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June 28, 2021 at 02:49PM
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[paper] RTN and BTI statistical compact modeling

G.Pedreira^a, J.Martin-Martinez^a, P.Saraza-Canflanca^b, R.Castro Lopez^b, R.Rodriguez^a, E.Roca^b, F.V.Fernandez^b, M.Nafria^a 

Unified RTN and BTI statistical compact modeling from a defect-centric perspective

Solid-State Electronics

Available online 25 June 2021, 108112

In Press, Journal Pre-proof

DOI: 10.1016/j.sse.2021.108112

a Universitat Autònoma de Barcelona (UAB), Electronic Engineering Department, REDEC group. Barcelona, Spain
b Instituto de Microelectrónica de Sevilla, IMSE-CNM, CSIC and Universidad de Sevilla, Spain

Abstract: In nowadays, deeply scaled CMOS technologies, time-dependent variability effects have become important concerns for analog and digital circuit design. Transistor parameter shifts caused by Bias Temperature Instability and Random Telegraph Noise phenomena can lead to deviations of the circuit performance or even to its fatal failure. In this scenario extensive and accurate device characterization under several test conditions has become an unavoidable step towards trustworthy implementing the stochastic reliability models. In this paper, the statistical distributions of threshold voltage shifts in nanometric CMOS transistors will be studied at near threshold, nominal and accelerated aging conditions. Statistical modelling of RTN and BTI combined effects covering the full voltage range is presented. 

The results of this work suppose a complete modelling approach of BTI and RTN that can be applied in a wide range of voltages for reliability predictions.