Nov 18, 2020

[paper] Verilog-A Ion Sensitive FET for pH Sensor

Megha Agrawal, Nidhi Agrawal, Alpana Agarwal and Anil K. Saini*
Modeling of Ion Sensitive Field Effect Transistor for pH Sensor using Verilog-A
 Recent Advancement in Communication System & Image Processing
RACISP-2012 at: BKBIET, Pilani

Thapar University, PATIALA – 147004, Punjab
*Central Electronics Engineering Research Institute, PILANI – 333031, Rajasthan

Abstract: ISFET semiconductor technology enables the design of true solid state pH sensor. An ISFET can be modeled by considering it as two fully uncoupled stages: an electronic stage i.e., the MOSFET which is the starting structure of the ISFET and an Electro-chemical stage i.e., the electrolyte–insulator interface which is pH dependent. This paper describes the modeling of ISFET for pH measurement using Verilog A which is compatible with cadence environment. Any change in pH directly affects the threshold voltage of ISFET. To measure this change in pH, ISFET is configured in such a way so that change in threshold voltage can be directly detected. For this purpose a sensing read-out has been designed using Gate complementary ISFET/MOSFET pair (CIMP) technique. Simulated result shows good linearity between output voltage of sensing readout circuit with pH variation for the range of 1 to12. The ISFET is thermally instable due to semiconductor properties and pH dependency on temperature, which in turn affects the pH reading of the solution at a temperature other than room temperature with slope of +0.69mV/0C, +1.25mV/0C and +1.60mV/0C respectively for pH= 4, for pH=7 and for pH=10.
Fig: a) n-channel ISFET structure and b) its equivalent electric circuit [ref]

Acknowledgment: The work is financially supported by Department of Information Technology, Ministry of Communication & Information Technology, Government of India, under SMDP-VLSI (Phase II) project.

[ref] Sergio Martinoia, Giuseppe Massobrio, “A Behavioral Macromodel of the ISFET in SPICE,” Sensors and Actuators B, Vol. 62, pp. 182–189, 2000

Appendix A

// Verilog-A Code for ISFET [ref]
`include "constants.vams"
`include "disciplines.vams"
module ISFET(ref,gm,ph);
inout ref,gm,ph;
electrical ref,gm,ph;
real EPH;
real T;
electrical node;
electrical x,y;
// PARAMETERS FOR ISFET
parameter real NAv = 6.023E26; //Avogadros constant(1/MOLE)
// ISFET geometrical parameters
parameter real DIHP =0.1E-9;
parameter real DOHP =0.3E-9;
//ISFET electrochemical parameters
parameter real KA = 15.8;
parameter real KB = 63.1E-9;
parameter real KN = 1E-10;
parameter real Nsil = 3.0E+18;
parameter real Nnit = 2.0E+18;
parameter real Cbulk = 0.1;
parameter real epso = 8.85E-12;
parameter real epsihp = 32; //relative permittivity of the Inner Helmholtz layer
parameter real epsohp = 32; //relative permittivity of the Outer Helmholtz layer
parameter real epsw = 78.5; //relative permittivity of the bulk electrolyte solution
//Reference-electrode electrochemical parameters
parameter real Eabs = 4.7; //absolute potential of the standard hydrogen electrode
parameter real Erel = 0.2;
parameter real Phim = 4.7; //work function of the metal back contact
parameter real Philj = 1E-3; //liquid-junction potential difference between the ref
solution and the electrolyte
parameter real Chieo = 3E-3; //surface dipole potential
real ET; //THERMAL COFFICIENT
real sq;
real CH, CD, CEQ, CB;
real Eref;

analog begin
T= $temperature;
ET= (`P_Q /(`P_K * T));
sq = sqrt(8*`P_EPS0*epsw*`P_K * T);
CB = (NAv*Cbulk);
CH = ((`P_EPS0*epsihp*epsohp) / (epsohp*DIHP + epsihp*DOHP));
CD = (sq*ET*0.5)*sqrt(CB);
CEQ = 1/(1/CD + 1/CH);
V(ref,node) <+ Eabs - Phim - Erel + Chieo + Philj;
Eref = V(ref,node);
V(x)<+ log(KA*KB)+4.6*V(ph);
V(y)<+ log(KA)+2.3*V(ph);
V(gm,node) <+ (`P_Q / CEQ) * (Nsil * ((limexp(-2 * V(gm,node) * ET)– limexp
(V(x))) / (limexp(-2 * V(gm,node) * ET) + limexp(V(y)) * limexp(-1 * V
(gm,node)*ET) + limexp(V(x)))) + Nnit*((limexp(-1 * V(gm,node)*ET))/(limexp(-1* V(gm,node)*ET)
+ (KN/KA) * limexp(V(y)))));
end
capacitor #(.c(CEQ)) Cq(node,gm);
resistor #(.r(1G)) RP1(x,gnd);
resistor #(.r(1G)) RP2(y,gnd);
resistor #(.r(1k)) RPH(ph,gnd);
endmodule

Nov 17, 2020

[paper] Editorial Special Section on ESSDERC

IEEE TED, Vol. 67, No. 11, November 2020

Mid-September 2020, we were supposed to celebrate in Grenoble the 50th anniversary of the European SolidState Device Research Conference and European Solid-State Circuits Conference (ESSDERC-ESSCIRC), which is the most important European conference dedicated to solid-state devices and circuits. However, in April 2020, more than one-third of the global population was under severe lock-down as a result of the protective public health measures imposed by the different governments, states, or provinces. Because of the COVID-19 pandemic, the ESSDERC-ESSCIRC organizing and steering committees, together with the sponsoring SSCS and EDS IEEE societies, decided to reschedule the in-person conference to September 6–9, 2021, in Grenoble, to add new virtual “Educational Events” held on September 14 and 15, 2020 (presentations available till October 16, 2020, at https://www.esscirc-essderc2020.org/) as well as to invite the ESSDERC-ESSCIRC research community to submit publications to the IEEE TRANSACTIONS ON ELECTRON DEVICES (TED) and to the IEEE SOLID-STATE CIRCUITS LETTERS (SSC-L), respectively, in a brief format. All of these initiatives met great success. Especially, more than 47 TED submissions were received and reviewed, and 32 papers were accepted and have been included in this dedicated section of the November TED issue.

We would like to thank all the authors for taking this opportunity to keep the ESSDERC-ESSCIRC momentum, all the IEEE reviewers for their reactivity, and all the ESSDERC-ESSCIRC sponsors for their trust in this difficult time. Let us think with a positive mind, and acknowledge that this experience opens a new and fruitful collaboration between ESSDERC and TED.

We hope you will enjoy reading these high-quality papers. Stay safe

FRANCOIS ANDRIEU, TPC Chair
CEA-Leti
Université Grenoble Alpes
38054 Grenoble, France

GIOVANNI GHIONE, Editor-in-Chief
Dipartimento di Elettronica e Telecomunicazioni
Politecnico di Torino
10129 Torino, Italy
Editorial Special Section on ESSDERC
 IEEE TED, Vol. 67, No. 11, November 2020
  1. Generalized Constant Current Method for Determining MOSFET Threshold Voltage M. Bucher, N. Makris, and L. Chevas pp.4559
  2. Performance and Low-Frequency Noise of 22-nm FDSOI Down to 4.2 K for Cryogenic Applications (Invited Paper) B. Cardoso Paz, M. Cassé, C. Theodorou, G. Ghibaudo, T. Kammler, L. Pirro, M. Vinet, S. de Franceschi, T. Meunier, and F. Gaillard pp.4563
  3. A Method for Series-Resistance-Immune Extraction of Low-Frequency Noise Parameters in Nanoscale MOSFETs A. Tataridou, G. Ghibaudo, and C. Theodorou pp.4568
  4. Analytical Model for Interface Traps-Dependent Back Bias Capability and Variability in Ultrathin Body and Box FDSOI MOSFETs W. Chen, L. Cai, X. Liu, and G. Du pp.4573
  5. Polarization Independent Band Gaps in CMOS Back-End-of-Line for Monolithic High-Q MEMS Resonator Confinement R. Hudeczek and P. Baumgartner pp.4578
  6. Out-of-Equilibrium Body Potential Measurement on Silicon-on-Insulator With Deposited Metal Contacts M. Alepidis, A. Bouchard, C. Delacour, M. Bawedin, and I. Ionica pp.4582
  7. Evaluation of High-Temperature High-Frequency GaN-Based LC-Oscillator Components A. Ottaviani, P. Palacios, T. Zweipfennig, M. Alomari, C. Beckmann, D. Bierbüsse, J. Wieben, J. Ehrler, H. Kalisch, R. Negra, A. Vescan, and J. N. Burghartz pp.4587
  8. Analysis of Gate-Metal Resistance in CMOS-Compatible RF GaN HEMTs R. Y. ElKashlan, R. Rodriguez, S. Yadav, A. Khaled, U. Peralagu, A. Alian, N. Waldron, M. Zhao, P. Wambacq, B. Parvais, and N. Collaert pp.4592
  9. Characterization and TCAD Modeling of Mixed-Mode Stress Induced by Impact Ionization in Scaled SiGe HBTs N. Zagni, F. M. Puglisi, G. Verzellesi, and P. Pavan pp.4597
  10. Hot-Electron Effects in AlGaN/GaN HEMTs Under Semi-ON DC Stress A. Minetto, B. Deutschmann, N. Modolo, A. Nardo, M. Meneghini, E. Zanoni, L. Sayadi, G. Prechtl, S. Sicre, and O. Häberlen pp.4602
  11. Vertically Replaceable Memory Block Architecture for Stacked DRAM Systems by Wafer-on-Wafer (WOW) Technology S. Sugatani, N. Chujo, K. Sakui, H. Ryoson, T. Nakamura, and T. Ohba pp.4606
  12. Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays T. Zanotti, C. Zambelli, F. M. Puglisi, V. Milo, E. Pérez, M. K. Mahadevaiah, O. G. Ossorio, C. Wenger, P. Pavan, P. Olivo, and D. Ielmini pp.4611
  13. IGZO-Based Compute Cell for Analog In-Memory Computing—DTCO Analysis to Enable Ultralow-Power AI at Edge D. Saito, J. Doevenspeck, S. Cosemans, H. Oh, M. Perumkunnil, I. A. Papistas, A. Belmonte, N. Rassoul, R. Delhougne, G. Kar, P. Debacker, A. Mallik, D. Verkest, and M. H. Na pp.4616
  14. Array-Level Programming of 3-Bit per Cell Resistive Memory and Its Application for Deep Neural Network Inference Y. Luo, X. Han, Z. Ye, H. Barnaby, J.-s. Seo, and S. Yu pp.4621
  15. Ultrahigh-Density 3-D Vertical RRAM With Stacked Junctionless Nanowires for In-Memory-Computing Applications M. Ezzadeen, D. Bosch, B. Giraud, S. Barraud, J.-P. Noël, D. Lattard, J. Lacord, J. M. Portal, and F. Andrieu pp.4626
  16. Thermal Stress-Aware CMOS–SRAM Partitioning in Sequential 3-D Technology S. M. Salahuddin, E. Dentoni Litta, A. Gupta, R. Ritzenthaler, M. Schaekers, J.-L. Everaert, H. Yu, A. Vandooren, J. Ryckaert, M.-H. Na, and A. Spessot pp.4631
  17. Cryogenic Operation of Thin-Film FDSOI nMOS Transistors: The Effect of Back Bias on Drain Current and Transconductance M. Cassé, B. Cardoso Paz, G. Ghibaudo, T. Poiroux, S. Barraud, M. Vinet, S. de Franceschi, T. Meunier, and F. Gaillard pp.4636
  18. Enhanced Ultraviolet Avalanche Photodiode With 640-nm-Thin Silicon Body Based on SOI Technology I. Sabri Alirezaei, N. Andre, and D. Flandre pp.4641
  19. TCAD Study of VLD Termination in Large-Area Power Devices Featuring a DLC Passivation L. Balestra, S. Reggiani, A. Gnudi, E. Gnani, J. Dobrzynska, and J. Vobecký pp.4645
  20. Analysis of MIS-HEMT Device Edge Behavior for GaN Technology Using New Differential Method R. Kom Kammeugne, C. Leroux, J. Cluzel, L. Vauche, C. Le Royer, R. Gwoziecki, J. Biscarrat, F. Gaillard, M. Charles, E. Bano, and G. Ghibaudo pp.4649
  21. Influence of Substrate Resistivity on Porous Silicon Small-Signal RF Properties G. Godet, E. Augendre, J. Lugo-Alvarez, H. Jacquinot, F. X. Gaillard, T. Lorne, E. Rolland, T. Taris, and F. Servant pp.4654
  22. Free Carrier Mobility, Series Resistance, and Threshold Voltage Extraction in Junction FETs N. Makris, M. Bucher, L. Chevas, F. Jazaeri, and J.-M. Sallese pp.4658
  23. Local Variability Evaluation on Effective Channel Length Extracted With Shift-and-Ratio Method J. P. Martinez Brito and S. Bampi pp.4662
  24. Charge-Based Model for the Drain-Current Variability in Organic Thin-Film Transistors Due to Carrier-Number and Correlated-Mobility Fluctuation A. Nikolaou, G. Darbandy, J. Leise, J. Pruefer, J. W. Borchert, M. Geiger, H. Klauk, B. Iniguez, and A. Kloes pp.4667
  25. Macromodel for AC and Transient Simulations of Organic Thin-Film Transistor Circuits Including Nonquasistatic Effects J. Leise, J. Pruefer, A. Nikolaou, G. Darbandy, H. Klauk, B. Iniguez, and A. Kloes pp.4672
  26. Compact Modeling and Behavioral Simulation of an Optomechanical Sensor in Verilog-A H. Elmi Dawale, L. Sibeud, S. Regord, G. Jourdan, S. Hentz, and F. Badets pp.4677
  27. TCAD Simulation Framework of Gas Desorption in CNT FET NO2 Sensors S. Carapezzi, S. Reggiani, E. Gnani, and A. Gnudi pp.4682
  28. Conductance in a Nanoribbon of Topologically Insulating MoS2 in the 1T Phase V. Sverdlov, A.-M. B. El-Sayed, H. Kosina, and S. Selberherr pp.4687
  29. Vt Extraction Methodologies Influence Process Induced Vt Variability: Does This Fact Still Hold for Advanced Technology Nodes? M. S. Bhoir, T. Chiarella, J. Mitard, N. Horiguchi, and N. R. Mohapatra pp.4691
  30. Multidomain Negative Capacitance Effect in P(VDF-TrFE) Ferroelectric Capacitor and Passive Voltage Amplification K. J. Singh, A. Bulusu, and S. Dasgupta pp.4696
  31. Monte Carlo Comparison of n-Type and p-Type Nanosheets With FinFETs: Effect of the Number of Sheets F. M. Bufler, D. Jang, G. Hellings, G. Eneman, P. Matagne, A. Spessot, and M. H. Na pp.4701
  32. Impact of Width Scaling and Parasitic Series Resistance on the Performance of Silicene Nanoribbon MOSFETs M. Poljak pp.4705

[book] Emerging Trends in Terahertz Solid-State Physics and Devices by Springer Nature https://t.co/d6ic3XhucH. https://t.co/gaEUA16nMZ #semi https://t.co/N1Gve7JdIy



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November 17, 2020 at 03:59PM
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Fwd: Webinar on Material Growth, Characterization of Semiconductors and Device Applications Through Atomistic TNL TCAD


We, Tech Next Lab jointly with IEEE are organizing online Webinar on Material Growth, Characterization of Semiconductors and Device Applications Through Atomistic TNL TCAD. You may register on below given link and forward webinar link to other participants who are interested:

 

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Nov 16, 2020

What Is a Graphene Field Effect Transistor (#GFET)?

 



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