Aging Model for ASAP 7nm Predictive PDK

Neha Gupta¹, Lomash Chandra Acharya¹, Mahipal Dargupally¹, Khoirom Johnson Singh², Amit Kumar Behera¹, Johan Euphrosine³, Sudeb Dasgupta¹, Anand Bulusu¹

Aging Model Development for ASAP 7 nm Predictive PDK: Application in Aging-Aware Performance Prediction of Digital Logic and ADCs in Data Acquisition System

IEEE ISVLSI (2025)

DOI: 10.1109/ISVLSI65124.2025.11130265

1 Indian Institute of Technology, Roorkee, (IN)
2 Dhanamanjuri University, Manipur (IN)
3 Google, Tokyo (J)

Abstract: As semiconductor technology advances to sub- 10nm nodes, Design Technology Co-Optimization (DTCO) has emerged as an essential paradigm for co-optimizing processes and design methodologies. Although the ASAP 7nm Predictive PDK (Process Design Kit), which is a free and open-source academic PDK developed by the Arizona State University (ASU) research team, is a useful open-source platform for digital design research, it lacks key DTCO features such as reliability modeling, aging resilience, and security-aware co-design. In this article, we present our developed aging model for ASAP 7nm Predictive PDK and utilize it to evaluate the impact of transistor aging on the performance of digital timing logic and a memory cell which provides timing feedback from a DTCO point-of-view concerning standard cells and other reference circuit designing. In this work, different logic gates, benchmark circuits, N-stage ring oscillator and 6T SRAM bitcell are used as the representative of digital logic and memory cell, respectively. We further utilize our developed aging model to predict performance of an analog-to-digital converter in data acquisition systems. The developed aging model would be released for the research community for further improvement in design reliability and technology enhancement along with OPENROAD Tool flow.

Fig. (a) Flow chart for representing steps required to develop Verilog-A aging model 

for ASAP 7nm Predictive PDK (FinFET) process. 

(b) Inclusion of the developed aging model to incorporate aging impact in static timing analysis (STA).

FOSSEE eSim Marathon – Circuit Design & Simulation with IHP SG13G2

Design, Simulate, Showcase

Unlock Open-Source VLSI Design  using eSim + IHP SG13G2 OpenPDK!!!

The eSim Marathon - Circuit Design & Simulation with IHP SG13G2 is a nationwide circuit design competition where participants use eSim, an open-source EDA tool developed by FOSSEE, IIT Bombay, to design and simulate circuits using the IHP OpenPDK for 130nm SG13G2 BiCMOS technology from IHP Microelectronics, Germany.

Key Highlights:

• Tool Used: eSim - a free and open-source alternative to commercial circuit design tools 
• OpenPDK Used: IHP SG13G2 - enables design of analog, digital, and RF circuits at 130 nm BiCMOS.
• Objective: Design, simulate, and submit functional analog/digital/mixed-signal circuits.
• Eligibility: Open to individuals - students, hobbyists, and early-career professionals.
• Learning Outcomes: Participants gain hands-on VLSI design experience using a real foundry OpenPDK, develop schematics, run simulations, and build documentation - entirely with open tools.

Register < https://esim-marathon.netlify.app/register/ >

Timeline

Date	Activity	Description
1 Sept. - 15 Sept. 2025	Registration for the Marathon	Complete the participation form
16 Sept. 2025	Marathon Inauguration Webinar	FOSSEE Team will introduce through eSim, IHP and Marathon process
16 Sept. - 23 Sept. 2025	Literature Survey	Participants need to research the topic available in papers/journals on the web
23 Sept. 2025	Report Submission	Submit one-page research conclusion and circuit implementation plan
23 Sept. - 5 Oct. 2025	Implementation	Design, characterise and simulate using eSim platform
5 Oct. - 8 Oct. 2025	Report Submission & Documentation	Upload reference and actual circuit/waveform using eSim
25 Oct. 2025	Result Declaration (Provisional)	Announcement of provisional results

[paper] Human Language to Analog Layout

Ali Hammoud, Chetanya Goyal, Sakib Pathen, Arlene Dai, Anhang Li, Gregory Kielian,
and Mehdi Saligane

Human Language to Analog Layout Using GLayout Layout Automation Framework

ACM/IEEE MLCAD 

https://doi.org/10.1145/3670474.3685971

Abstract: Current approaches to Analog Layout Automation apply ML techniques such as Graph Convolutional Neural Networks (GCN) to translate netlist to layout. While these ML approaches have proven to be effective, they lack the powerful reasoning capabilities, an intuitive human interface, and standard evaluation benchmarks that have been improving at a rapid development pace in Large Language Models (LLMs). The GLayout framework introduced in this work translates analog layout into an expressive, technology generic, compact text representation. Then, an LLM is taught to understand analog layout through fine-tuning and in-context learning using Retrieval Augmented Generation (RAG). The LLM is able to successfully layout unseen circuits based on new information provided in-context. We train 3.8, 7, and 22 Billion parameter quantized LLMs on a dataset of less than 50 unique circuits, and text documents providing layout knowledge. The 22B parameter model is tuned in 2 hours on a single NVIDIA A100 GPU. The open-source evaluation set is proposed as an automation benchmark for LLM layout automation tasks, and ranges from 2-transistor circuits to aΔΣ ADC. The 22B model completes 70% of the tasks in the evaluation set, and passes DRC and LVS verification on 44% of evaluations with verified correct blocks up to 4 transistors in size.

FIG: Full process of translating user prompt to a final layout.

Acknowledgments: The authors would like to thank the open-source community for their support.

 

[paper] Differential Aging-Aware Static Timing Analysis

Lomash Chandra Acharya, Neha Gupta, Khoirom Johnson Singh, Mahipal Dargupally, Neeraj Mishra, 

Arvind Kumar Sharma, Ajoy Mondal, Venkatraman Ramakrishnan, 

Sudeb Dasgupta, and Anand Bulusu

DAAS: Differential Aging-Aware STA for Precise Timing Closure With Reduced Design Margin

in IEEE Transactions on Device and Materials Reliability

DOI: 10.1109/TDMR.2025.3603098

1.) Department of Electronics and Communication Engineering, IIT Roorkee (IN)
2.) Department of Electronics, Dhanamanjuri University, Imphal (IN)
3.) Department of Electronics and Electrical Engineering, BITS Pilani (IN)
4.) Semiconductor Technology and Systems Department, IMEC (B)
5.) EDA Group, Texas Instruments, Bengaluru (IN)
6.) OnSemi Technology, Bengaluru (IN)

Abstract : This article introduces DAAS, a Differential Aging-Aware Static Timing Analysis methodology built upon an Effective Current Source Model (ECSM). The primary objective is to achieve precise timing closure for digital integrated circuits while minimizing design margins. To achieve this goal, we employ a one-time aging simulation using a single MOS device-based approach. This approach estimates the change in threshold voltage (Vth) denoted by (Vth) in a MOS device under diverse operating conditions, such as supply voltage and temperature, in the presence of aging. The estimated value of (Vth) is then used to update the model coefficient of timing models for various combinational gates. These updated models are utilized to generate differential aging-aware standard cell library data in an industry-standard Liberty format. This data can be seamlessly integrated into common STA environments like Synopsys PrimeTime, facilitating the estimation of timing closure for designs with different blocks operating at varying voltages and temperature conditions. The proposed methodology eradicates the need for circuit-level aging simulation to generate differential aging-aware standard cell library data. It demonstrates an average error of 2.5% compared to conventional aging simulation on standard cells using the STMicroelectronics (STM) 28nm CMOS process. Furthermore, the method significantly reduces the required number of SPICE/aging simulations by approximately 99.984% to generate differential aging-aware standard cell library characterization data. Further, we demonstrate the versatility of the proposed DAAS methodology for the generation of standard cell library data in the case of PDK migration and different device variants without performing full SPICE-level simulations.

FIG: Representation of the approach used to model a standard cell 

with transistor topology of a buffer and its terminal transitions as a test case.

[Education Corner] Tinkering with CMOS Circuits

P. Kinget

Tinkering with CMOS Circuits at the Lunch Table with MOSbius

[Education Corner]

in IEEE Solid-State Circuits Magazine, vol. 17, no. 3, pp. 72-78, Summer 2025

doi: 10.1109/MSSC.2025.3583537

Abstract: Experimental validation is a critical step in any engineering discipline and doing lab experiments is an essential part of the formation of an engineer. Creating relevant experiments to train integrated-circuit designers has become difficult due to the lack of appropriate components. We designed the MOSbius chip and adapter PCB so learners can perform circuit labs with MOS transistor topologies that are relevant to modern transistor-level IC design. With MOSbius, students can experiment with customized CMOS circuits early on – without the challenges, delays, and cost of designing a custom integrated circuit. Yet, MOSbius serves as a great steppingstone towards full custom IC design courses.

Fig: An overview of the MOSbius platform. Students design and realize transistor-level MOS circuits

using on-chip-style topologies and evaluate them experimentally.

Acknowledgment: Many thanks to the MOSbius crew of enthusiastic current and former students: Longyi Li, Yunfan Gao, Zhuo Chen, Petar Barac, Ray Xu, Hongzhe Jiang, Cade Gleekel, Nico de la Cruz, Rosnel Alejandro Leyva-Cortes, Yuechen He, Jingde Hu, Qizhe Wu, Jingrui Li, Xianglin Pu, Yuntao Guo, and Andrew Chon. Thanks to Apple, Inc. for fabrication funding through the Columbia ELEN E6350 VLSI Design Lab course. Thanks to Yannis Tsividis (Columbia), John Pigott (NXP), Babak Soltanian (Tayen.Ai), Jianxun Zhu (Analog Devices, Inc.), Jared Zerbe (Apple), Eric Smith (Apple), Doug Mercer (ADI), and many others for engaging discussions and sharing of ideas.