Oct 3, 2025

[paper] THz MOST based on aligned carbon nanotube arrays

Jianshuo Zhou, Zipeng Pan, Li Ding, Lin Xu, Xiaohan Cheng, Haitao Li, Fenfa Yao, Chuanhong Jin, Maguang Zhu, Lijun Liu, Huiwen Shi, Zhiyong Zhang and Lian-Mao Peng
Terahertz metal–oxide–semiconductor transistors based on aligned carbon nanotube arrays. 
Nat Electron (2025)
DOI: https://doi.org/10.1038/s41928-025-01463-6

1. Key Laboratory for the Physics and Chemistry of Nanodevices and Center for Carbon-based Electronics, Peking University
2. Hunan Institute of Advanced Sensing and Information Technology, Xiangtan University, Xiangtan, China
3. Chongqing Institute of Carbon-based Integrated Circuits, Peking University, Chongqing, China
4. Academy for Advanced Interdisciplinary Studies, Peking University, Beijing, China
5. State Key Laboratory of Silicon and Advanced Semiconductor Materials, Zhejiang University, Hangzhou, China
6. Frontiers Science Center for Nano-optoelectronics, Peking University, Beijing, China


Abstract: Films of aligned semiconducting carbon nanotubes could be used to build complementary metal–oxide–semiconductor field-effect transistors for digital integrated circuits and radio-frequency transistors for terahertz analogue integrated circuits. However, the operating frequencies of such devices remains too low for potential application in the sixth generation of wireless communications. Here we report metal–oxide–semiconductor field-effect transistors that are based on aligned carbon nanotube films and have a cut-off frequency beyond 1 THz. By optimizing gate structures and fabrication processes, we create devices with a gate length of 80 nm that have a carrier mobility of over 3,000 cm2 V−1 s−1, as well as an on-state current of 3.02 mA µm−1, a peak transconductance of 1.71 mS μm−1 at a bias of −1 V, and a saturation velocity of 3.5 × 107 cm s−1. By introducing a Y-shaped gate, we also create devices with gate lengths of 35 nm that have an extrinsic cut-off frequency (fT) of up to 551 GHz and a maximum oscillation frequency (fmax) of 1,024 GHz. Finally, we use devices with a gate length of 50 nm to fabricate mmWave-band (30 GHz) radio-frequency amplifiers that have a gain of up to 21.4 dB.

Fig: Characteristics of Y-gate structure in A-CNT MOSFETs.

Acknowledgements: This work is supported by the National Key Research & Development Program (grant number 2022YFB4401603 to L.D.) and Natural Science Foundation of China (grant numbers 62171004 to L.D., 92477201 to L.-M.P. and 62225101 to Z.Z.).

Sep 29, 2025

[Thesis] Verilog-A MOSFET Model for Analog IC Design

Master Thesis by Alba Gallego Velázquez
Defended: July 1, 2025
Technical University of Crete, Chania
Tutor: Prof. Matthias Bucher

Abstract: The present thesis sets out the development and implementation of a compact model of a MOSFET, based on the theoretical EKV model, and implemented using the Verilog-A language. The utilization of simulation and compilation environments, such as the open server OpenVAF and Ngspice, is instrumental in facilitating the effective execution of the work. The construction of a model that can perform the function of an nMOS or a pMOS nanometric operating in a saturated state is facilitated by these. In this model, physical dependencies and second-order effects are incorporated, ensuring the attainment of continuous expressions for all inversion regions. The model's behavior is validated against experimental data by means of simulation. This results in an accurate, compact and versatile model, which is suitable for supporting integrated analog circuits designs with a wide range of values for the inversion coefficient.
Fig: Normalized (𝐺𝑚𝑠 ·𝑈𝑡)/ID of the nMOS vs. the inversion coefficient (IC)




[paper] Gate stack engineering of 2D transistors

Yeon Ho Kim, Donghun Lee, Woong Huh, Jaeho Lee, Donghyun Lee, 
Gunuk Wang, Jaehyun Park, Daewon Ha and Chul-Ho Lee*
Gate stack engineering of two-dimensional transistors.
Nat Electron 8, 770–783 (2025)
DOI: 10.1038/s41928-025-01448-5

* Laboratory of Emerging Electronics & optoElectronics, SNU / julianus95@snu.ac.kr

Abstract: Gate stack engineering has helped enable aggressive device scaling in silicon complementary metal–oxide–semiconductor technology. Two-dimensional (2D) materials are a potential replacement for silicon in next-generation electronics. However, creating gate stacks that are capable of effective and reliable channel control with such materials is inherently challenging owing to the lack of compatible dielectrics and fabrication methods. Here we explore the development of gate stack engineering technologies for two-dimensional transistors. We benchmark key performance metrics for two-dimensional metal–oxide–semiconductor gate stacks against current silicon-based technologies, as well as the targets set by the International Roadmap for Devices and Systems. We also highlight recent advances in ferroelectric-embedded gate stacks, which offer additional functionalities and could be of use in the development of high-speed non-volatile memories and logic-in-memory devices, as well as low-power transistors. Finally, we consider the technical challenges that need to be addressed to develop advanced electronic technologies based on two-dimensional transistors.
FIG: CMOS logic technology roadmap and potential of angstrom-scale 2D transistors

Acknowledgment: This research was supported by the Ministry of Science and ICT under the Next-Generation Intelligent Semiconductor Technology Development Project and the Nano and Material Technology Development Program (Future Technology Labs). The graduate researchers received additional support from BK21 Four and the SNU Graduate School of AI Semiconductor.


Sep 13, 2025

[Online Publications] 22nd MOS-AK/ESSERC Workshop in Munich (D) on Sept. 8 2025



Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
MOS-AK/ESSERC Workshop
Munich, Sept.8, 2025

The consecutive, 22nd MOS-AK Workshop has been organized as an integral part of 51st ESSERC in Munich (D) on Sept. 8 2025. The MOS-AK workshop publications [1-6], with individually assigned DOI numbers, are available online at:

The development of open-source Process Design Kits (PDKs) is crucial for democratizing access to advanced semiconductor technologies. IHP's OpenPDK initiative bridges the gap between academia, startups, and the semiconductor industry by offering a fully open and manufacturable SG13G2 BiCMOS OpenPDK for analog/RF, mixed-signal, and digital IC applications. Aligning with the EU Chips Act, this initiative emphasizes open collaboration to overcome economic and technical barriers in semiconductor innovation. The workshop introduces SG13G2 OpenPDK and Free and Open-Source Software (FOSS) tools for IC designs, including Verilog-A devices, schematic capture, SPICE simulation, layout, physical verification in advanced design flow up to final typeout.

To learn more about IHP OpenPDK Initiative and its Certified Design Courses, visit online depositories as listed below:

Open-Source Digital Design Course: https://github.com/OS-EDA/Course
  • Full RTL-to-GDSII workflow using OpenROAD and SG13G2 PDK
  • Feedback integrated via GitHub & live sessions
  • Trial run Feb 2025: 15 on-site participants selected from 85+ applicants
Open-Source Analog Design Course: https://github.com/IHP-GmbH/IHP-AnalogAcademy
  • Hands-on design with SG13G2 PDK; Strong emphasis on analog/RF practice, focused on the layout and verification, including process variation analysis of analog/RF ICs
  • Explored designs: Bandgap, 50 GHz PA, SAR ADC
  • Tools: Ngspice, Xyce, Xschem, Qucs, Klayout
  • Trial run June 2025: with 16 on-site participants selected from 80+ applicants
MOS-AK Workshop References:

[1] M. Yazici and R. Scholz, "IHP OpenPDK Roadmap", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113282.


[2] Árpád Bűrmen, "The OpenVAF Verilog-A Compilerfor the OpenPDK Ecosystem", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113774.


[3] M. Volker, "User-friendly FDTD EM Workflow for IHP OpenPDK with Automatic Meshing", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113926.


[4] Mike Brinson, "Building Component Libraries for Use with the IHP OpenPDK and FOSS Tools", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113932.

[5] Mirjana Videnović-Mišić, "Analog IC Flow Automatization", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113935.

[6] Ralph Steiner Vanha, "MOS SizingTool – A Single Transistor Simulator", presented at the MOS-AK/ESSERC Workshop Munich 2025, Munich, Germany, Sep. 13, 2025. doi: 10.5281/zenodo.17113946.

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To view this discussion visit https://groups.google.com/d/msgid/mos-ak/CALp-Rj8%2B6scvmo1NPVGtxpK2jmNYjrjQoQQL6LZM90fE3hnxZQ%40mail.gmail.com.

Sep 12, 2025

[paper] MicroLEDs SPICE Model

Sultan El Badaoui1,2, Patrick Le Maitre1, Anthony Cibié1, Julia Simon1, Aurélien Lardeau-Falcy1, 
Jeremy Bilde1, Louwenn Cherruault1, Manon Arch1, Michael Pelissier1, Yannis Le Guennec2
SPICE Modeling of GaN MicroLEDs for Optical Communication
Journal of the Society for Information Display, 2025; 0:1–16
DOI 10.1002/jsid.2105

1 Univ. Grenoble Alpes, CEA LETI, Minatec, Grenoble (F)
2 Univ. Grenoble Alpes, CNRS, Grenoble-INP, GIPSA-lab, Grenoble (F)

Abstract: With the rapid expansion of data centers, there is a growing demand for high data-rate, energy-efficient optical links over short distances. One potential technology for this application is Gallium-Nitride (GaN) based microlight emitting diodes (μLEDs), thanks to their compact size, high-speed operation, and ease of manufacturability. During the development of these μLEDs, modeling plays an essential role in optimizing their performance. In this paper, we present various models to estimate both the static and dynamic performance of GaN μLEDs of various sizes. We then propose a methodology to integrate these models into a unified equivalent circuit model, enabling the simulation of the full response of the μLED. Finally, we implement this unified model in a circuit-simulation-compatible module and replicate the experimental setups within a simulation software to evaluate the module's ability to accurately simulate the μLED's response.



FIG: (a) SEM image of a 50-μm μLED, showing the GSG pad configuration and the grid contact over the μLED
(b) Schematic of the stack of the μLEDs 
9c) Simulation setup used to for transient simulation

Acknowledgments: This work is part of the IPCEI Microelectronics and Connectivity and was supported by the French Public Authorities within the frame of France 2030 and by the Institut Carnot CEA-Leti.