Yeon Ho Kim, Donghun Lee, Woong Huh, Jaeho Lee, Donghyun Lee,
Gunuk Wang, Jaehyun Park, Daewon Ha and Chul-Ho Lee*
Gate stack engineering of two-dimensional transistors.
Nat Electron 8, 770–783 (2025)
DOI: 10.1038/s41928-025-01448-5
* Laboratory of Emerging Electronics & optoElectronics, SNU / julianus95@snu.ac.kr
Abstract: Gate stack engineering has helped enable aggressive device scaling in silicon complementary metal–oxide–semiconductor technology. Two-dimensional (2D) materials are a potential replacement for silicon in next-generation electronics. However, creating gate stacks that are capable of effective and reliable channel control with such materials is inherently challenging owing to the lack of compatible dielectrics and fabrication methods. Here we explore the development of gate stack engineering technologies for two-dimensional transistors. We benchmark key performance metrics for two-dimensional metal–oxide–semiconductor gate stacks against current silicon-based technologies, as well as the targets set by the International Roadmap for Devices and Systems. We also highlight recent advances in ferroelectric-embedded gate stacks, which offer additional functionalities and could be of use in the development of high-speed non-volatile memories and logic-in-memory devices, as well as low-power transistors. Finally, we consider the technical challenges that need to be addressed to develop advanced electronic technologies based on two-dimensional transistors.
FIG: CMOS logic technology roadmap and potential of angstrom-scale 2D transistors
Acknowledgment: This research was supported by the Ministry of Science and ICT under the Next-Generation Intelligent Semiconductor Technology Development Project and the Nano and Material Technology Development Program (Future Technology Labs). The graduate researchers received additional support from BK21 Four and the SNU Graduate School of AI Semiconductor.
