Oct 23, 2023

[paper] Lorentzian noise spectra in compact models

Nikolaos Makris*†, Loukas Chevas* and Matthias Bucher*
Verilog-A based implementation of Lorentzian noise spectra in compact models
26th International Conference on Noise and Fluctuations - ICNF
17th-20th October 2023 - Grenoble - France
DOI10.1109/ICNF57520.2023.10472771

* School of Electrical & Computer Engineering, Technical University of Crete (TUC), GR-73100 Chania, Greece        European University on Responsible Consumption and Production (EURECA-PRO) (Joint affiliation)
† Institute of Electronic Structure and Laser, Foundation for Research and Technology-Hellas (IESL-FORTH), GR-71110 Heraklion, Greece


Abstract:In this paper, a simple Verilog-A implementation of Lorentzian noise spectra is introduced that can be used in compact models for the frequency-domain simulation of low-frequency noise in electronic devices. For this purpose, a thermal noise source is combined with a low-pass filter as realized using laplace_nd Verilog-A function in order to achieve Lorentzian noise behavior. This modeling approach can be implemented in any Verilog-A compact model and provides the means for bias-dependent Lorentzian trap modeling. This approach is evaluated in commercial simulator. Application examples are provided to demonstrate the capabilities of this approach.
FIG: Bias dependent model implemented in the EKV3 MOSFET model

Acknowledgements: This work was co-funded by the ERASMUS+ Programme of the European Union (Contract number: 101004049 - EURECA-PRO - EAC-A02-2019 / EAC-A02-2019-1). This research has been co-financed by the European Regional Development Fund of the European Union and Greek national funds through the Operational Program Competitiveness, Entrepreneurship and Innovation, under the call RESEARCH - CREATE - INNOVATE (project code: T2EDK-00340).


Oct 17, 2023

[mos-ak] [2nd Announcement] 16th International MOS-AK Workshop Silicon Valley, Dec. 13, 2023


Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
16th International MOS-AK Workshop
Silicon Valley, December 13, 2023

2nd Announcement and C4P

The 16th International MOS-AK Workshop on Compact/SPICE Modeling will take place on Dec.13, 2023, in timeframe of IEDM and Q4 CMC Meetings. This event is coorganized by Keysight Technologies, our local host and partner, and the Extended MOS-AK TPC Committee. We invite you to join us for MOS-AK workshop and learn from the experts in the field of SPICE/Verilog-A modeling.

Planned 16th International MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:
  • Compact Modeling (CM) of the electron devices
  • Advances in semiconductor technologies and processing
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • Open Source (FOSS) TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, Organic TFT, CMOS and SOI-based memory
  • Microwave, RF device modeling, high voltage device modeling
  • Device level modeling for Agroelectronics, Bio/Med, IoT applications
  • Device cryogenic operation for Quantum Computing 
  • Nanoscale semiconductor devices/circuits and its reliability/ageing
  • Technology R&D, DFY, DFT and IC Designs
  • Foundry/Fabless Interface Strategies, Open Access PDK(eg: Skywater 130nm CMOS, IHP 130nm RF BiCMOS) 
Online Abstract Submission is open (any related enquiries can be sent to abstracts@mos-ak.org)

Online Free Registration is open (any related enquiries can be sent to registration@mos-ak.org)

Important Dates: 
W.Grabinski for Extended MOS-AK Committee

WG171023

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/mos-ak/CALp-Rj9Pfr1tboqZtiTGqb-%3D4gxMweegQ9zNWGtX%3Dm%2Bc6%3DitWg%40mail.gmail.com.

[Call for Book Chapters] Perovskite Solar Cells

Call for Book Chapters:
Book Title: Perovskite Solar Cell

Table of Content
  • Introduction to Perovskite Solar Cells
  • Fundamentals of Perovskite Materials
  • Fabrication Techniques
  • Characterization Methods
  • Perovskite Solar Cell Physics
Important Dates:
Chapter proposal submission deadline: 15th November 2023
Notification of Acceptance: 21st November 2023
Full Chapter submission: 30th January 2024
Acceptance/Rejection Notification: 10th February 2024

Prospective authors are requested to submit their chapter proposals/full chapters. 
<https://www.routledge.com/our-customers/authors/publishing-guidelines>
There are no publication fees for a chapter submitted to this book publication. All submitted chapters will be peer reviewed. For chapter proposals/full chapter submission and queries: tdsubash2007@gmail.com


[webinar] IEEE SCV-EDS: Investigating quantum speed limits with superconducting qubits

The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is hosting Prof. Meenakshi Singh. The title of the lecture is ‘Investigating quantum speed limits with superconducting qubits’

When: Friday, Oct. 20, 2023 – 9am to 10am (PDT)
Where: This is an online event and attendees can participate via Zoom.

Registration or Send an email to hiuyung.wong at ieee.org to get the zoom link indicating if you are IEEE member, IEEE EDS member, IEEE Student member

Abstract: The speed at which quantum entanglement between qubits with short range interactions can be generated is limited by the Lieb-Robinson bound. Introducing longer range interactions relaxes this bound and entanglement can be generated at a faster rate. The speed limit for this has been analytically found only for a two-qubit system under the assumption of negligible single qubit gate time. We seek to demonstrate this speed limit experimentally using two superconducting transmon qubits. Moreover, we aim to measure the increase in this speed limit induced by introducing additional qubits (coupled with the first two). Since the speed up grows with additional entangled qubits, it is expected to increase as the system size increases. This has important implications for large-scale quantum computing.

Speaker Bio: Dr. Singh is an experimental physicist with research focused on quantum thermal effects and quantum computing. She graduated from the Indian Institute of Technology with an M. S. in Physics in 2006 and received a Ph. D. in Physics from the Pennsylvania State University in 2012. Her Ph. D. thesis was focused on quantum transport in nanowires. She went on to work at Sandia National Laboratories on Quantum Computing as a post-doctoral scholar. She is currently an Associate Professor in the Department of Physics at the Colorado School of Mines. At Mines, her research projects include measurements of spin-orbit coupling in novel materials and thermal effects in superconducting hybrids. She recently received the NSF CAREER award to pursue research in phonon interactions with spin qubits in silicon quantum dots.

Oct 16, 2023

[IHP Career] Research associate for Open PDK Development

Research associate for Open PDK Development (m/f/d)
Developer for Open Source Process Design Kits for SiGe-BiCMOS technolog

Job-ID: 7064/23 | Department: Technology | Salary: as per tariff TV-L | Working time: 40h/week (part-time work option) | Limitation: initially 2 years with option of extension | Entry Date: as soon as possible

The position:
As a member of the group Research & Prototyping Service you will develop Process Design Kit (PDK) for IHP’s BiCMOS technologies and new future technology modules. Your detailed tasks will include programming (e.g. pcells or run decks for DRC and LVS) for commercial as well as open-source tools for ASIC design environments.
Devices descriptions, user guides and test cases are important aspects of your work, too. Implementation of new devices and investigations into new design tools and flows, this includes adaption of tools, will give this position room interesting development opportunities.

Your profile:
You hold a Master's degree in computer science with strong background in semiconductors, physics or electrical engineering. Knowledge in semiconductor devices and programming are of advantage. Your specialized knowledge preferably covers ASIC design environment like Cadence Virtuoso, Mentor/Siemens/Tanner, KeySight ADS or the open source tools like OpenROAD/OpenLane.
Furthermore, you have skills for programming in scripting languages (e.g. Python, Perl or TCL). You are well organized and always keep the overview even with many parallel projects. Thanks to your skillful communication, you are a binding and reliable contact person for our partners.
You are also a strong team player. We are looking for a team member, who is able to structure his or her own work and to bring a well-organized and systematic way of working into the cooperation with creative minds. You are an ideal match for this position, when you have experimental, analytical and problem-solving skills, very strong communicative skills and the ability to quickly learn how to operate the latest technical equipment including various software. It is necessary that you confidently handle the English language. Knowledge of the German language is welcome.
The consolidating of German language skills is expected and highly encouraged, for example in in-house language courses and intensive courses.