[paper] Compact Model for MoS2 FETs

A physics-based compact model for MoS2 field-effect transistors

considering the band-tail effect and contact resistance

Yuan Liu¹, Jiawei Zeng², Zeqi Zhu¹, Xiao Dong² and WanLing Deng³

Japan Society of Applied Physics; Accepted Manuscript online 11 September 2020

¹Guangdong University of Technology, Guangzhou, Guangdong, CHINA

²Jinan University, Guangzhou, Guangdong, CHINA
³Electronic Engineering, Jinan University, Guangzhou, GuangDong, 510630, CHINA

Abstract: In this paper, we present a compact surface-potential-based drain current model in molybdenum disulfide (MoS2) field-effect transistors (FETs). Considering variable range hopping (VRH) transport via band-tail states in MoS2 transistors, an explicit solution for surface potential has been derived and it provides a good description over different regions of operation by comparisons with numerical data. Based on charge-sheet model (CSM) which applies to drift-diffusion transport, the current expression including contact resistance and velocity saturation effect is developed. Furthermore, the presented model is validated and shows a good agreement with experiment data for MoS2 FETs. Keywords: molybdenum disulfide (MoS2), surface potential, current expression.

Fwd: September 2020 Newsletter: Planet-Scale Processing of Silicates

September 2020 Newsletter: Planet-Scale Processing of Silicates In the eastern Sierra Nevada mountains, near Mammoth Lakes, California, is a geological phenomenon: a cliffside lined with thousands of 10-20 meter tall pillars of basalt. The organized rock columns are so incongruous with the surrounding high altitude pine forest that they seem supernatural. Shepherds who frequented the area in the 1800's named it the "Devil's Woodpile." Today, it's a popular park called the Devils Postpile National Monument. To a MEMS engineer, this odd rock cliff bears a striking resemblance to the columnar grains in thin film PZT or ZnO. What a mind bender to see familiar shapes from SEM images towering overhead. Like PZT or ZnO, a special set of environmental conditions created the Devils Postpile. It was not, however, the result of grain growth; instead, the Postpile formed from a pool of lava which then cracked into a network of polygons as it cooled. (More like misprocessed thick photoresist!) A scale factor of 20 million: PZT with columnar grains (top) compared to basalt columns (bottom). Sources: http://dx.doi.org/10.1021/acsami.6b16470, http://www.nps.gov/depo On top of the Devils Postpile, one particular area has a smooth surface which reveals the cross-sections of the polygonal columns, 50-100 cm in width. This most unusual stone patio was formed by the water, pressure, and motion of a passing Ice Age glacier, a massive-scale version of chemical mechanical polishing (CMP). Basalt rock is primarily composed of SiO2 (45-52% by weight) and other metal oxides, such as TiO2, Al2O3 and MgO; all familiar MEMS materials, just in a much larger format. Ancient CMP: cross-section of basalt columns, polished flat by a glacier. Note the fine lines that were created by grit trapped in the moving glacier. Four kilometers from the Postpile is the stunning 30 meter tall Rainbow  Falls, etched through two layers of volcanic rock. The top masking layer of rock is harder than the thick underlayer of softer rhyodacite. Water pouring over the edge erodes the soft rock at a faster rate, leaving a re-entrant cliff face and thereby creating a beautiful waterfall. An idle thought while hiking on a hot summer day: Is geology just a planet-scale version of MEMS processes? Please note: AMFitzgerald's business operations are continuing normally despite COVID *and* California wildfires. Where to Meet Us Virtually SEMI/MSIG Executive Congress Virtual More information October 6-8 and 13-15, at 8:00 am – 10:30 am PDT  About Us A.M. Fitzgerald & Associates, LLC ("AMFitzgerald") provides complete solutions for MEMS product development. Our full service engineering capabilities include: custom MEMS design to specification, semi-custom RocketMEMS® pressure sensors, process integration, prototype and short-run fabrication, multiphysics finite element modeling, foundry selection and transfer with support through production, and technology strategy consulting.  We turn your ideas into silicon - find out how For more information call: (650) 347-MEMS / (650) 347-6367 CONNECT WITH US! ‌

A.M. Fitzgerald & Associates, LLC | 700 Airport Blvd. Suite 210, Burlingame, CA 94010 Unsubscribe wladek.grabinski@gmail.com Update Profile | About our service provider Sent by klm@amfitzgerald.com powered by Try email marketing for free today!

[paper] Low-voltage, Non-volatile, Compound-semiconductor Memory Cell

Room-temperature Operation of Low-voltage, Non-volatile, Compound-semiconductor Memory Cell

Ofogh Tizno, Andrew R. J. Marshall, Natalia Fernández-Delgado, Miriam Herrera, Sergio I. Molina
and Manus Hayne

Scientific Reports volume 9, Article number: 8950 (2019) 

DOI: 10.1038/s41598-019-45370-1

Abstract: Whilst the different forms of conventional (charge-based) memories are well suited to their individual roles in computers and other electronic devices, flaws in their properties mean that intensive research into alternative, or emerging, memories continues. In particular, the goal of simultaneously achieving the contradictory requirements of non-volatility and fast, low-voltage (low-energy) switching has proved challenging. Here, we report an oxide-free, floating-gate memory cell based on III-V semiconductor heterostructures with a junctionless channel and non-destructive read of the stored data. Non-volatile data retention of at least 10000s in combination with switching at ≤2.6 V is achieved by use of the extraordinary 2.1 eV conduction band offsets of InAs/AlSb and a triple-barrier resonant tunnelling structure. The combination of low-voltage operation and small capacitance implies intrinsic switching energy per unit area that is 100 and 1000 times smaller than dynamic random access memory and Flash respectively. The device may thus be considered as a new emerging memory with considerable potential.

FIG: Device structure a) Schematic of the processed device with control gate (CG), source (S) and drain (D) contacts (gold). The red spheres represent stored charge in the floating gate (FG). b) Cross-sectional scanning transmission electron microscopy image showing the high quality of the epitaxial material, the individual layers and their heterointerfaces.

Simulation Methods: The nextnano software package was utilised for mathematically modelling the energy band diagram of the memory device structure reported here, taking into account strain and piezoelectricity. Within this work, a self-consistent Schrödinger solver was used along with the Poisson and drift–diffusion equations to calculate the electron densities at equilibrium and under bias.

The Industry’s First SoC FPGA Development Kit Based on the #RISC-V Instruction Set Architecture is Now Available | Microchip Technology https://t.co/1CCwP6GR3h #semi https://t.co/TKw7mFqOcC

The Industry’s First SoC FPGA Development Kit Based on the #RISC-V Instruction Set Architecture is Now Available | Microchip Technology https://t.co/1CCwP6GR3h #semi pic.twitter.com/TKw7mFqOcC

— Wladek Grabinski (@wladek60) September 16, 2020

---

from Twitter https://twitter.com/wladek60

September 16, 2020 at 04:32PM
via IFTTT

FreePDK15: Process Design kit for 15-nm FinFETs

Development of a Predictive Process Design kit for 15-nm FinFETs: FreePDK15 

Kirti Bhanushali, Chinmay Tembe, and W. Rhett Davis 

arXiv:2009.04600v1 [cs.AR] 9 Sep 2020

Abstract: FinFETs are predicted to advance semiconductor scaling for sub-20nm devices. In order to support their introduction into research and universities it is crucial to develop an open source predictive process design kit. This paper discusses in detail the design process for such a kit for 15nm FinFET devices, called the FreePDK15. The kit consists of a layer stack with thirteen-metal layers based on hierarchical-scaling used in ASIC architecture, Middle-of-Line local interconnect layers and a set of Front-End-of-Line layers. The physical and geometrical properties of these layers are defined and these properties determine the density and parasitics of the design. The design rules are laid down considering additional guidelines for process variability, challenges involved in FinFET fabrication and a unique set of design rules are developed for critical dimensions. Layout extraction including modified rules for determining the geometrical characteristics of FinFET layouts are implemented and discussed to obtain successful Layout Versus Schematic checks for a set of layouts. Moreover, additional parasitic components of a standard FinFET device are analyzed and the parasitic extraction of sample layouts is performed. These extraction results are then compared and assessed against the validation models.

FIG: Middle-of-Line layers used as interconnects

Acknowledgment: The authors would like to thank Paul Franzon at NC State University. The authors would like to thank Mentor Graphics, since this project would not have been possible without their generous gift of supporting funds and Calibre licenses. The authors would also like to thank Tarek Ramadan, Ahmed Hammed Fathy, Omar El-Sewefy, Ahmed El-Kordy, Hend Wagieh and the team at Mentor Graphics for development of the first set of design rules and their constant support.In addition, the authors would like to thank and acknowledge Alexandre Toniolo at Nangate for clarifying the vision of MOL layers. We would also like to thank Cadence designsystems for use of the virtuoso software and Synopsys Inc.for use of Pycell studio. The authors would also like to thanks Vikas Sharma for P-Cells, Vidyanandgouda Patil for design rule fixes and Namrata Sampat for help cleaning up the distribution.