[paper] 3D Vertical JL GAA Si Nanowire Transistors

Chhandak Mukherjee¹, Guilhem Larrieu² and Cristell Maneuxsup¹

Compact Modeling of 3D Vertical Junctionless Gate-all-around Silicon Nanowire Transistors

EuroSOI-ULIS 2020, Sep 2020, Caen (F)

¹IMS Laboratory, University of Bordeaux, France

²LAAS-CNRS, Université de Toulouse, France 

HAL: hal.archives-ouvertes.fr/hal-02869216

Abstract: This paper presents a physics based, computationally efficient compact modeling approach for 3D vertical gate-all-around junctionless nanowire transistor (JLNT) arrays designed for future high performance computational logic circuit. The model features an explicit continuous analytical form adapted for a 14 nm channel JLNT technology and has been validated against extensive characterization results on a wide range of JLNT geometry, depicting good accuracy. Finally, preliminary logic circuit simulations have been performed for benchmarking performances of transistor logic circuits, such as inverters and ring oscillators, designed using the developed model.

Fig: The vertical JLNT: (a) SEM image of nanowire arrays, 

(b) single nanowire showing its (c) gate formation 

Acknowledgement: This work is supported by ANR under Grant ANR-18- CE24-0005-01

[webinar] Differentiated FDSOI for mmWave Solutions

WEBEX by IEEE EDS Santa Clara Valley/San Francisco Chapter

Differentiated Fully Depleted SOI (FDSOI) Technology 

for Highly Efficient and Integrated mmWave Wireless Connectivity Solution

Speaker: Dr. Anirban Bandyopadhyay,  Director, Strategic Marketing and Business Analytics, GLOBALFOUNDRIES, Inc., Santa Clara, CA

Friday, July 24, 2020 at 12PM – 1PM PDT

WEBEX ONLY: Click Here to Attend

Abstract: The emergence of enhanced mobile broadband (eMBB) connectivity based on mmWave 5G and the emerging prospect of broadband internet to using non-terrestrial mmwave backhaul using low earth orbit (LEO) satellite generated huge interest in the entire telecommunication ecosystem. While mmwave allows huge bandwidth of channels to enable enhanced broadband, it also poses a lot of technical challenges in terms of coverage, generating enough transmitted power efficiently particularly in the uplink, system cost & scaling and long term reliability of the hardware system particularly for infrastructure including Satellite born systems. Current talk will focus on how Silicon technologies based on differentiated fully depleted SOI (FDSOI) can address the above challenges by enabling a highly efficient and integrated radio without compromising on the mmWave performance and reliability. Talk will highlight the technology Figures of Merits (FOMs) for a mmwave phased array system and how a differentiated FDSOI technology platform compares with other silicon technologies in terms of devices and circuits.

Speaker Bio: Dr. Anirban Bandyopadhyay is the Director, Strategic Marketing and Business Analytics within the Mobility & Wireless Infrastructure Business Unit of GLOBALFOUNDRIES, USA. His work is currently focused on hardware architecture & technology evaluations for emerging RF and mmWave applications. Prior to joining GLOBALFOUNDRIES, he was with IBM Microelectronics, New York and with Intel, California where he worked on different areas like RF Design Enablement, Silicon Photonics, signal integrity in RF & Mixed signal SOC’s. Dr. Bandyopadhyay did his PhD in Electrical Engineering from Tata Institute of Fundamental Research, India and Post-Doctoral research at Nortel, Canada and at Oregon State University, USA. He represents Global Foundries in different industry consortia on RF/mmWave applications and is a Distinguished Lecturer of IEEE Electron Devices Society.

More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

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IEEE SSCS-EDS Distinguished Talks (Webinar) Systematic Design of Analog CMOS Circuits Dr. Paul Jespers, UCLouvain, Louvain-la-Neuve, Belgium July 09th, 13h30 (Brasilia Time, GMT-3) https://t.co/d3HL96l2xT https://t.co/FQOFMq4FJG #paper https://t.co/zelqSxMxGI

IEEE SSCS-EDS Distinguished Talks (Webinar)
Systematic Design of Analog CMOS Circuits
Dr. Paul Jespers, UCLouvain, Louvain-la-Neuve, Belgium
July 09th, 13h30 (Brasilia Time, GMT-3)https://t.co/d3HL96l2xT https://t.co/FQOFMq4FJG#paper pic.twitter.com/zelqSxMxGI

— Wladek Grabinski (@wladek60) June 29, 2020

from Twitter https://twitter.com/wladek60

June 29, 2020 at 11:04AM
via IFTTT

Creating A Custom ASIC With The First Open Source PDK: The FOSSi foundation now reports on a new, open PDK project launched by Google and SkyWater Technology https://t.co/6G78tYz4c1 #model https://t.co/NOCZS6YMr5

Creating A Custom ASIC With The First Open Source PDK: The FOSSi foundation now reports on a new, open PDK project launched by Google and SkyWater Technology https://t.co/6G78tYz4c1#model pic.twitter.com/NOCZS6YMr5

— Wladek Grabinski (@wladek60) June 26, 2020

from Twitter https://twitter.com/wladek60

June 26, 2020 at 02:14PM
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Neurotransistor MatLab Code

Eunhye Baek, Nikhil Ranjan Das, Carlo Vittorio Cannistraci, Taiuk Rim, Gilbert Santiago Cañón Bermúdez, Khrystyna Nych, Hyeonsu Cho, Kihyun Kim, Chang-Ki Baek, Denys Makarov, Ronald Tetzlaff, Leon Chua, Larysa Baraban and Gianaurelio Cuniberti

Intrinsic plasticity of silicon nanowire neurotransistors for dynamic memory and learning functions

Nat Electron (2020). 

DOI: 10.1038/s41928-020-0412-1

Abstract: Neuromorphic architectures merge learning and memory functions within a single unit cell and in a neuron-like fashion. Research in the field has been mainly focused on the plasticity of artificial synapses. However, the intrinsic plasticity of the neuronal membrane is also important in the implementation of neuromorphic information processing. Here we report a neurotransistor made from a silicon nanowire transistor coated by an ion-doped sol–gel silicate film that can emulate the intrinsic plasticity of the neuronal membrane. The neurotransistors are manufactured using a conventional complementary metal–oxide–semiconductor process on an 8-inch (200 mm) silicon-on-insulator wafer. Mobile ions allow the film to act as a pseudo-gate that generates memory and allows the neurotransistor to display plasticity. We show that multiple pulsed input signals of the neurotransistor are non-linearly processed by sigmoidal transformation into the output current, which resembles the functioning of a neuronal membrane. The output response is governed by the input signal history, which is stored as ionic states within the silicate film, and thereby provides the neurotransistor with learning capabilities.

FIG: Illustration of the structural similarity between the ion migration in the neurotransistor (left) and the membrane of a neuron cell in which the ionic current was modulated by a membrane potential (Vmemb) change in the case of the action potential (right)

Code availability: The MatLab code that supports the mathematical model in this article is available
at https://github.com/eunhye8747/MatLab-Code-Neurotransistor

Acknowledgements: This research was supported by the German Excellence Initiative via the Cluster of Excellence EXC1056 Center for Advancing Electronics Dresden (CfAED) and the MSIP (Ministry of Science, ICT and Future Planning), Korea, under the ICT Consilience Creative Program (IITP-R0346-16-1007) supervised by the IITP (Institute for Information & communications Technology Promotion). We acknowledge support from the Initiative and Networking Fund of the Helmholtz Association of German Research Centers through the International Helmholtz Research School for Nanoelectronic Networks (IHRS NANONET) (no. VH‐KO‐606) and German Research Foundation (DFG) via grants MA 5144/9-1, MA 5144/13-1 and MA 5144/14-1; BA4986/7−1, BA4986/8−1. Finally, we thank the INSA-DFG Bilateral Exchange Programme for financial support (IA/ DFG/2018/138, 12 April 2018). The authors thank S. Oswald (IFW Dresden) for the X-ray photoemission spectroscopy analysis of the ion-doped hybrid silicate films and M. Park (NamLab, Dresden) for the insightful discussion about the ionic polarization in the film. We thank R. Nigmetzianov (TU Dresden) for the film analysis.