[paper] 3D Vertical JL GAA Si Nanowire Transistors

Chhandak Mukherjee¹, Guilhem Larrieu² and Cristell Maneuxsup¹

Compact Modeling of 3D Vertical Junctionless Gate-all-around Silicon Nanowire Transistors

EuroSOI-ULIS 2020, Sep 2020, Caen (F)

¹IMS Laboratory, University of Bordeaux, France

²LAAS-CNRS, Université de Toulouse, France 

HAL: hal.archives-ouvertes.fr/hal-02869216

Abstract: This paper presents a physics based, computationally efficient compact modeling approach for 3D vertical gate-all-around junctionless nanowire transistor (JLNT) arrays designed for future high performance computational logic circuit. The model features an explicit continuous analytical form adapted for a 14 nm channel JLNT technology and has been validated against extensive characterization results on a wide range of JLNT geometry, depicting good accuracy. Finally, preliminary logic circuit simulations have been performed for benchmarking performances of transistor logic circuits, such as inverters and ring oscillators, designed using the developed model.

Fig: The vertical JLNT: (a) SEM image of nanowire arrays, 

(b) single nanowire showing its (c) gate formation 

Acknowledgement: This work is supported by ANR under Grant ANR-18- CE24-0005-01