Implementation and quality testing for HICUM/L2 compact models implemented in Verilog-A https://t.co/xXnNhTZcgb #papers

Implementation and quality testing for HICUM/L2 compact models implemented in Verilog-A https://t.co/xXnNhTZcgb #papers

— Wladek Grabinski (@wladek60) July 25, 2016

from Twitter https://twitter.com/wladek60

July 25, 2016 at 02:11PM
via IFTTT

VeSFET is a twin-gate device with 3D vertical terminals and channel based on SOI conventional CMOS https://t.co/AGiySLvzUj #papers

VeSFET is a twin-gate device with 3D vertical terminals and channel based on SOI conventional CMOS https://t.co/AGiySLvzUj #papers

— Wladek Grabinski (@wladek60) July 22, 2016

from Twitter https://twitter.com/wladek60

July 22, 2016 at 03:18PM
via IFTTT

Leti-UTSOI Compact Model

The Leti-UTSOI compact model is the only one to be totally dedicated to the FDSOI technology. In its recent version, the Leti-UTSOI model has reached its maturity. In collaboration with STM, its robustness was validated by successfully complying with the full test suite recommended by the CMC. The Leti-UTSOI model is now currently used at STM in the IC design division. It is now available in an industrial design-kit. The documentation and some model cards (typical) are available below:

• Model_Description_UTSOI_v113_light.pdf (336.82 kB)
• Lib_Hspice_UTSOIv113.lib (11.55 kB)
• Lib_Eldo_UTSOIv113.lib (11.55 kB)

The Leti-UTSOI Verilog-A code can also be obtained contacting LETI UTSOI Developers.

[read more...]

Leti-UTSOI Compact Model

The Leti-UTSOI compact model is the only one to be totally dedicated to the FDSOI technology. In its recent version, the Leti-UTSOI model has reached its maturity. In collaboration with STM, its robustness was validated by successfully complying with the full test suite recommended by the CMC. The Leti-UTSOI model is now currently used at STM in the IC design division. It is now available in an industrial design-kit. The documentation and some model cards (typical) are available below:

• Model_Description_UTSOI_v113_light.pdf (336.82 kB)
• Lib_Hspice_UTSOIv113.lib (11.55 kB)
• Lib_Eldo_UTSOIv113.lib (11.55 kB)

The Leti-UTSOI Verilog-A code can also be obtained contacting LETI UTSOI Developers.

[read more...]

LETI Compact Modeling Links

LETI compact modeling links points to the Workshops and Conferences:

MOS-AK (Modeling of Systems and Parameter Extraction Working Group)
S3S (IEEE SOI-3D Subthreshold Microelectronics Technology Unified Conference)

IEDM (IEEE International Electron Devices Meeting)
VLSI  (29th International Conference on VLSI Design)
SISPAD (Simulation of Semiconductor Processes and Devices)

[read more...]