Bruni, Italo, Mariane Petraglia, and Fabián Olivera
Area-efficient nanoampere current reference employing
a temperature-controlled n-MOS pseudo-resistor
AEU IJ EC (2026): 156642.
DOI: 10.1016/j.aeue.2026.156642
Abstract: This paper presents a CMOS current reference topology that avoids the use of large-area resistors by using a temperature-controlled pseudo-resistor. The proposed technique for achieving a reference current consists of applying proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) voltages to the drain and gate of an n-MOS EKV-based pseudo-resistor, respectively, thereby stabilizing its current against temperature variations. Two current reference design versions, namely D01 and D02, were implemented using a 180 nm technology. Extensive post-layout simulation results for design D01 show a typical reference current of 6.30 nA, an average temperature coefficient (TC) of 414 ppm/C (nominal 219 ppm/C) across a range from −40C to 120C, and a line regulation (LR) of 11.76 %/V. To improve LR, design D02 was developed, achieving a significantly optimized LR of 0.33 %/V while maintaining a typical current of 6.22 nA and an average TC of 401 ppm/C (nominal 191 ppm/C) over the same temperature range. The area-efficient technique enables compact silicon areas of 0.0018 mm2 and 0.0020 mm2 for D01 and D02, respectively.
FIG: Schematics of the CTAT voltage generator topologies: .a) 3T; b.) 6T
and its layout implementation of the current reference designs: c.) D01; d.) D02.
Acknowledgment: This work was supported in part by the Brazilian research funding agencies CNPq, FAPERJ, and Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - Brasil (CAPES) Finance Code 001; by grant 307092/2025-9, funded by CNPq/MCTI/FNDCT N∘18/2024; and by grant E-26/204.222/2025 (SEI-260003/020616/2025), founded by FAPERJ JCNE .
