[workshop] QC:DCEP 2023

Workshop on

Quantum Computing: Devices, Cryogenic Electronics and Packaging

A Seasonal School of the IEEE Circuits & Systems Society

Tues/Wed, 24-25 October, 2023 at SEMI World Hdqtrs, Milpitas, CA USA

Welcome to the first year of this new Workshop from the IEEE Circuits and Systems Society, organized and run by three Silicon Valley IEEE chapters: Circuits and Systems, Electron Devices and Electronics Packaging.

QC:DCEP 2023 is planned to be a hybrid event, with both in-person and WebEx participation. Registration is now open. On-site seating is limited. Review the Advance Program.

The intent of this workshop is to bring together engineers of electrical, mechanical, materials and computer science disciplines and physicists to describe the state-of-the-art in all the interconnected fields and the opportunities and challenges for future generations of quantum computers.

Confirmed plenary and invited talks:

Technical Challenges facing Quantum Computing with Superconducting Transmon Qubits Dr. Daniel Tennant, Rigetting Computing		Superconducting Multi-Chip Module (SMCM) Rabindra N. Das, MIT Lincoln Laboratory
Introduction to Quantinuum and TKET Dr. Kathrin Spendier, Quantinuum		Understanding and Addressing Challenges in Superconducting Qubit Scale Jennifer Smith, UC-Santa Barbara
Integrated Quantum-Classical Applications with CUDA Quantum Dr. Jin-Sung Kim, NVIDIA		A 22nm FD-SOI-CMOS Scalable Quantum Processor SoC with Fully Integrated Control Electronics at 3.5K Dr. Imran Bashir, Equal1
Network Architecture for a Scalable Spin Qubit Processor Prof. Jonathan Baugh, Univ. of Waterloo		Quantum Computing with Silicon Spins Dr. Dominik Zumbuhl, Univ of Basel
Quantum Error Correction in Bosonic Qubits Marina Kudra, PhD, Intermodulation Products		Thermal Management Challenges in Cryogenic System Integration: Spin Qubit Biasing with a CMOS DAC at mK Temperature Lea Schreckenberg, Forschungszentrum Jülich GmbH

plus additional technical talks 

Drawings will be held for two GeForce RTX-4090 graphics cards, donated by NVIDIA — one will be awarded to an on-site speaker, while the other will be awarded to an on-site attendee. These new gaming accelerators for Windows PCs are not yet on sale. Need not be present to win. We invite you to register for QC:DCEP 2023 using our EventBrite site. Register today!

[C4P] 36th ICMTS 2024

36th International Conference on Microelectronic Test Structures

April 15-18, 2024, Edinburgh, Scotland

Looking for the best opportunity to present and discuss your ideas and results about test structures, measurements and characterization? This is your chance! Join the 36th ICMTS conference. A Tutorial Short Course will precede the main conference. Several of the best measurement, equipment design, and manufacturing experts, will participate in the equipment exhibition and presentations. The conference will bring together designers and users of test structures to discuss recent developments and future directions, in a one-track program, with convivial breaks allowing attendees to discuss and exchange viewpoints and challenges.

A Best Paper award will be presented by the Technical Program Committee. The conference is co-sponsored by the IEEE Electron Devices Society and all accepted papers, if presented, will be submitted for possible inclusion on IEEEXplore®. Original papers are solicited presenting new developments in topics relevant to ICMTS, including but not limited to, test structures, measurements, and results, in the following areas:

• Design
• Methodologies, Verification
• Within-die circuits for process characterization/monitoring
• Design enablement – Characterization and validation of digital and analog libraries
• Devices and Circuit Modelling
• Measurement techniques
• DC, AC and RF measurements: setup, test and analysis
• Reliability test - including thermal stability, failure analysis etc.
• Statistical analysis, variability, throughput increase, smart test strategies
• Use of machine learning and AI in analysis of data sets - parameter extraction etc.
• Wafer probing, within-die measurements, in-line metrology
• Throughput, testing strategies, yield enhancement and process control tests
• Applications
• Emerging memory technologies (single cell, arrays, and application in neural networks)
• Emerging transistor technologies for digital/analog/power applications
• Photonic devices - silicon integration, new displays (OLED, μ-displays)
• Flexible electronics and sensors (organic and inorganic materials)
• M(N)EMS, actuators, sensors, PV cells and other emerging devices

The author’s abstract submission consists of up to four pages in PDF format (font-embedded). The first page should include a title, a 50-word summary, author name(s), full address, contact number and e-mail of the lead author, and any preference for oral or poster session presentation. The body of the abstract should consist of one page of text (800 to 1000 words) and up to two pages of major figures and tables. The selection process will be based on the technical merit and will be highly weighted in favour of abstracts with high test structure content, giving a clear illustration of the test structure and including measurements and data analysis.

The abstract submission deadline is October 27th, 2023.

Abstracts can be submitted via the ICMTS 2024 website www.icmts.net using the “Abstract Submission” link on the front page. Notice of paper acceptance will be sent to the selected authors by 12th January 2024, with instructions for the expanded manuscript preparation for the conference proceedings. The deadline for submission of the final paper will be Early March, 2024 (TBC).

Please join the ICMTS LI group, if you have interest in all things test and measurement.

Details of the venue, hotel, registration, etc. will be posted when available at the ICMTS 2024 official website.

For further technical information, please contact the technical program chair:

Francesco Driussi, Università di Udine

3rd MFEM Community Workshop, October 26, 2023

MFEM is a free, open source, lightweight, scalable C++ library for finite element methods.

Features

• Arbitrary high-order finite element meshes and spaces.
• Wide variety of finite element discretization approaches.
• Conforming and nonconforming adaptive mesh refinement.
• Scalable from laptops to GPU-accelerated supercomputers.
• ... and many more.
• See MFEM Gallery, Publications, Videos and News pages.

MFEM is used in many projects, including BLAST, Cardioid, Palace, VisIt, RF-SciDAC, FASTMath, xSDK, and CEED in the Exascale Computing Project.

Annual workshop 

MFEM host an annual workshop and FEM@LLNL seminar series. The MFEM team has  announced the 3rd MFEM Community Workshop, which will take place on October 26, 2023, virtually, using Zoom for videoconferencing. The goal of the workshop is to foster collaboration among all MFEM users and developers, share the latest MFEM features with the broader community, deepen application engagements, and solicit feedback to guide future development directions for the project.

Registration
If you plan to attend, please register no later than October 19th. There is no registration fee. Zoom details will be distributed to participants prior to the event date. For questions, please contact the meeting organizers at mfem@llnl.gov.

[paper] Model for Cryo-CMOS Subthreshold Swing

Arnout Beckers, Jakob Michl, Alexander Grill, Member IEEE; Ben Kaczer, Marie Garcia Bardon, Bertrand Parvais, Bogdan Govoreanu, Kristiaan De Greve, Gaspard Hiblot, 

and Geert Hellings, Senior Member IEEE

Physics-Based and Closed-Form Model for Cryo-CMOS Subthreshold Swing

in IEEE Transactions on Nanotechnology, vol. 22, pp. 590-596, 2023,

DOI 10.1109/TNANO.2023.3314811.

IMEC, Leuven (B)

Institute for Microelectronics, TU Vienna (A)

Vrije Universiteit Brussel (B)

KU Leuven (B)

Abstract: Cryogenic semiconductor device models are essential in designing control systems for quantum devices and in benchmarking the benefits of cryogenic cooling for high-performance computing. In particular, the saturation of subthreshold swing due to band tails is an important phenomenon to include in low-temperature analytical MOSFET models, as it predicts theoretical lower bounds on the leakage power and supply voltage in tailored cryogenic CMOS technologies with tuned threshold voltages. Previous physics-based modeling required to evaluate functions with no closed-form solutions, defeating the purpose of fast and efficient model evaluation. Thus far, only the empirically proposed expressions are in closed form. This article bridges this gap by deriving a physics-based and closed-form model for the full saturating trend of the subthreshold swing from room down to low temperature. The proposed model is compared against experimental data taken on some long and short devices from a commercial 28-nm bulk CMOS technology down to 4.2 K.

FIG: (a) TEM picture of a mature imec technology node. (b) Electrostatic potential fluctuations near the channel/oxide interface. (c) Gaussian distributed depths of the potential wells. (d) Including the binding energy in the wells in the quantum picture gives a Laplace distribution of P(Eb). (e-f) Convolution (*) of P(Eb) with the sharp-edged 2-D DOS leads to a logistic/Fermi-like DOS function with an exponential tail.

[paper] Characterization and Modeling of SOI LBJTs at 4K

Yuanke Zhang, Yuefeng Chen, Yifang Zhang, Jun Xu, Chao Luo, and Guoping Guo

Characterization and Modeling of Silicon-on-Insulator 

Lateral Bipolar Junction Transistors at Liquid Helium Temperature

IEEE TED Vol. XX, No. XX, preprint arXiv:2309.09257 (2023).

University of Science and Technology of China (USTC), Hefei 230026, Anhui, China

CAS Key Lab ofQuantum Information, Hefei 230026, Anhui, China.

Abstract: Conventional silicon bipolars are not suitable for low-temperature operation due to the deterioration of current gain (β). In this paper, we characterize lateral bipolar junction transistors (LBJTs) fabricated on silicon-on insulator (SOI) wafers down to liquid helium temperature (4 K). The positive SOI substrate bias could greatly increase the collector current and have a negligible effect on the base current, which significantly alleviates β degradation at low temperatures. We present a physical-based compact LBJT model for 4 K simulation, in which the collector current (IC) consists of the tunneling current and the additional current component near the buried oxide (BOX)/silicon interface caused by the substrate modulation effect. This model is able to fit the Gummel characteristics of LBJTs very well and has promising applications in amplifier circuits simulation for silicon-based qubits signals.

Fig: IC (solid lines) and IB (dash lines) versus VBE of LBJT at different temperatures 

under (a) VBOX = 0 V; (b) VBOX = 12 V, VCE = 1 V.

Acknowledgement: The device fabrication was done by Prof. Zhen Zhang’s group in the Angstrom Microstructure Laboratory (MSL) at Uppsala University. Dr. Qitao Hu, Dr. Si Chen, Prof. Zhen Zhang are acknowledged for the device design and fabrication, and the technical staff of MSL are acknowledged for their process support.