Oct 28, 2021

[paper] SET and CMOS circuits

Tetsufumi Tanamoto1, and Keiji Ono2
Simulations of hybrid charge-sensing single-electron-transistors and CMOS circuits
Appl. Phys. Lett. 119, 174002 (2021)
DOI: 10.1063/5.0068555

1Department of Information and Electronic Engineering, Teikyo University (J)
2Advanced Device Laboratory, RIKEN (J)


Abstract: Single-electron transistors (SETs) have been extensively used as charge sensors in many areas, such as quantum computations. In general, the signals of SETs are smaller than those of complementary metal–oxide–semiconductor (CMOS) devices, and many amplifying circuits are required to enlarge the SET signals. Instead of amplifying a single small output, we theoretically consider the amplification of pairs of SETs, such that one of the SETs is used as a reference. We simulate the two-stage amplification process of SETs and CMOS devices using a conventional SPICE (Simulation Program with Integrated Circuit Emphasis) circuit simulator. Implementing the pairs of SETs into CMOS circuits makes the integration of SETs more feasible because of direct signal transfer from the SET to the CMOS circuits.

Fig: (a) Six transistor SRAM cells applied in the second-stage amplification 
(b) Time-dependent voltage behaviors of the SRAM setup of L = 90 nm  
(c) Replotting of (b) for L = 65 nm.


#Samsung to triple #foundry capacity



from Twitter https://twitter.com/wladek60

October 28, 2021 at 03:39PM
via IFTTT

#Apple joins as first public partner in new #imec research program



from Twitter https://twitter.com/wladek60

October 28, 2021 at 10:07AM
via IFTTT

Oct 27, 2021

[paper] Transistors Based on Lateral PtSe2 Heterostructures

Gaetano Calogero*, Damiano Marian, Enrique G. Marin**, Gianluca Fiori 
and Giuseppe Iannaccone
Physical insights on transistors based on lateral heterostructures 
of monolayer and multilayer PtSe2 via Ab initio modelling of interfaces
Sci Rep 11, 18482 (2021)
DOI: 10.1038/s41598-021-98080-y
  
Dipartimento di Ingegneria dell’Informazione, Università di Pisa  (I)
*Consiglio Nazionale delle Ricerche, Istituto per le Microelettronica e Microsistemi (I)
**Dipartimento Electronica, Facultad de Ciencias, Universidad de Granada (SP)

Abstract: Lateral heterostructures (LH) of monolayer-multilayer regions of the same noble transition metal dichalcogenide, such as platinum diselenide (PtSe2), are promising options for the fabrication of efficient two-dimensional field-effect transistors (FETs), by exploiting the dependence of the energy gap on the number of layers and the intrinsically high quality of the heterojunctions. Key for future progress in this direction is understanding the effects of the physics of the lateral interfaces on far-from-equilibrium transport properties. In this work, a multi-scale approach to device simulation, capable to include ab-initio modelling of the interfaces in a computationally efficient way, is presented. As an application, p- and n-type monolayer-multilayer PtSe2 LH-FETs are investigated, considering design parameters such as channel length, number of layers and junction quality. The simulations suggest that such transistors can provide high performance in terms of subthreshold characteristics and switching behavior, and that a single channel device is not capable, even in the ballistic defectless limit, to satisfy the requirements of the semiconductor roadmap for the next decade, and that stacked channel devices would be required. It is shown how ab-initio modelling of interfaces provides a reliable physical description of charge displacements in their proximity, which can be crucial to correctly predict device transport properties, especially in presence of strong dipoles, mixed stoichiometries or imperfections.
Fig: Block diagram of the multi-scale procedure. Bulk DFT calculations of the materials forming the LH are performed using a plane wave basis. The resulting Hamiltonians are then projected onto MLWF and used as building blocks to construct a LH Hamiltonian with an arbitrarily long channel. The resulting LH Hamiltonian is finally used as input in NanoTCAD ViDES to simulate LH-FETs in far-from-equilibrium conditions.

Acknowledgements: This work has been supported by the European Commission through the Horizon 2020 Framework Program, Future Emerging Technologies QUEFORMAL project (contract n. 829035). The authors thank Dr. Alessandro Fortunelli for useful discussions.

In #Germany talks are for an advanced few nm #Intel #fab



from Twitter https://twitter.com/wladek60

October 27, 2021 at 02:10PM
via IFTTT