[book] 75th Anniversary of the Transistor

75th Anniversary of the Transistor 

Arokia Nathan (Editor), Samar K. Saha (Editor), Ravi M. Todi (Editor)

ISBN: 978-1-394-20244-7 August 2023 Wiley-IEEE Press 464 Pages

Description: 75th Anniversary of the Transistor is a commemorative anniversary volume to celebrate the invention of the transistor. The anniversary volume was conceived by the IEEE Electron Devices Society (EDS) to provide comprehensive yet compact coverage of the historical perspectives underlying the invention of the transistor and its subsequent evolution into a multitude of integration and manufacturing technologies and applications.

The book reflects the transistor’s development since inception to the current state of the art that continues to enable scaling to very large-scale integrated circuits of higher functionality and speed. The stages in this evolution covered are in chronological order to reflect historical developments.

Narratives and experiences are provided by a select number of venerated industry and academic leaders, and retired veterans, of the semiconductor industry. 75th Anniversary of the Transistor highlights:

• Historical perspectives of the state-of-the-art pre-solid-state-transistor world (pre-1947) leading to the invention of the transistor
• Invention of the bipolar junction transistor (BJT) and analytical formulations by Shockley (1948) and their impact on the semiconductor industry
• Large scale integration, Moore’s Law (1965) and transistor scaling (1974), and MOS/LSI, including flash memories — SRAMs, DRAMs (1963), and the Toshiba NAND flash memory (1989)
• Image sensors (1986), including charge-coupled devices, and related microsensor applications

With comprehensive yet succinct and accessible coverage of one of the cornerstones of modern technology, 75th Anniversary of the Transistor is an essential reference for engineers, researchers, and undergraduate students looking for historical perspective from leaders in the field.

TABLE OF CONTENTS

Editor Biography xiii

Preface xv

1 The First Quantum Electron Device 1

Leo Esaki

2 IEEE Electron Devices Society: A Brief History 3

Samar K. Saha

3 Did Sir J.C. Bose Anticipate the Existence of p- and n-Type Semiconductors in His Coherer/Detector Experiments? 17

Prasanta Kumar Basu

4 The Point-Contact Transistor: A Revolution Begins 29

John M. Dallesasse and Robert B. Kaufman

5 On the Shockley Diode Equation and Analytic Models for Modern Bipolar Transistors 43

T. H. Ning

6 Junction-Less Field Effect Transistors: The First Transistor to be Conceptualized 51

Mamidala Jagadesh Kumar and Shubham Sahay

7 The First MOSFET Design by J. Lilienfeld and a Long Journey to Its Implementation 65

Hiroshi Iwai

8 The Invention of the Self-Aligned Silicon Gate Process 89

Robert E. Kerwin

9 The Application of Ion Implantation to Device Fabrication: The Early Days 95

Alfred U. MacRae

10 Evolution of the MOSFET: From Microns to Nanometers 101

Yuan Taur

11 The SOI Transistor 115

Sorin Cristoloveanu

12 FinFET: The 3D Thin-Body Transistor 135

Chenming Hu

13 Historical Perspective of the Development of the FinFET and Process Architecture 145

Digh Hisamoto

14 The Origin of the Tunnel FET 155

Gehan A. J. Amaratunga

15 Floating-Gate Memory: A Prime Technology Driver of the Digital Age 163

S. M. Sze

16 Development of ETOX NOR Flash Memory 179

Stefan K. Lai

17 History of MOS Memory Evolution on DRAM and SRAM 187

Mitsumasa Koyanagi

18 Silicon-Germanium Heterojunction Bipolar Transistors: A Retrospective 215

Subramanian S. Iyer and John D. Cressler

18.9 Some Parting Words (SSI) 235

19 The 25-Year Disruptive Path of InP/GaAsSb Double Heterojunction Bipolar Transistors 239

Colombo R. Bolognesi

20 The High Electron Mobility Transistor: 40 Years of Excitement and Surprises 253

Jesús A. del Alamo

21 The Thin Film Transistor and Emergence of Large Area, Flexible Electronics and Beyond 263

Yue Kuo, Jin Jang, and Arokia Nathan

22 Imaging Inventions: Charge-Coupled Devices 273

Michael F. Tompsett

23 The Invention and Development of CMOS Image Sensors: A Camera in Every Pocket 281

Eric R. Fossum

25 Creation of the Insulated Gate Bipolar Transistor 299

B. Jayant Baliga

26 The History of Noise in Metal-Oxide-Semiconductor Field-Effect Transistors 309

Renuka P. Jindal

27 A Miraculously Reliable Transistor: A Short History 323

Muhammad Ashraful Alam and Ahmed Ehteshamul Islam

28 Technology Computer-Aided Design: A Key Component of Microelectronics' Development 337

Siegfried Selberherr and Viktor Sverdlov

29 Early Integrated Circuits 349

Willy Sansen

30 A Path to the One-Chip Mixed-Signal SoC for Digital Video Systems 355

Akira Matsuzawa

31 Historical Perspective of the Nonvolatile Memory and Emerging Computing Paradigms 369

Ming Liu

32 CMOS Enabling Quantum Computing 379

Edoardo Charbon

33 Materials and Interfaces: How They Contributed to Transistor Development 387

Bruce Gnade

34 The Magic of MOSFET Manufacturing 393

Kelin J. Kuhn

35 Materials Innovation: Key to Past and Future Transistor Scaling 403

Tsu-Jae King Liu and Lars P. Tatum

36 Germanium: Back to the Future 415

Krishna C. Saraswat

References 428

Index 431

[paper] Logic Without CMOS

Jonathan Hall and Manus Hayne

Logic Without CMOS: A III-V Semiconductor, Single Charge Carrier Approach to Digital Logic

WOCSDICE-EXMATEC 2023, Palermo (Italy), 21-25 May 2023

Department of Physics, Lancaster University, Lancaster, United Kingdom

Abstract: A new patent-pending approach to digital logic devices is proposed as an alternative to complimentary metal-oxide-semiconductor (CMOS) logic. A novel III-V semiconductor digital logic device combines both the “n” and “p” equivalents of CMOS into a single heterostructure device using just one type of charge carrier. The device, which forms an inverter, consists of two charge-accepting channel layers which sandwich a central electron (or hole) reservoir. Under zero bias the charge remains in the reservoir with both channel layers absent of free charge carriers (off state). Once a bias is applied to the gate, charge is either pushed into the bottom channel (negative bias) or pulled into the top channel (positive bias) turning one channel on whilst the other remains off. Thus, the complementary behaviour of logic, in which one part of the logic element is on and the other is off, is achieved without the asymmetry of hole and electron mobility. Proof of concept devices have been designed in both the well documented GaAs/AlxGa1-xAs system and in the 6.1Å family of semiconductors. One-dimensional, room temperature energy-band simulations using nextnano++ (software for semiconductor devices) [1] have shown effective and symmetric logic function at low voltage and an excess of 1,000× charge density ratio between the two channels under operation. Proof of concept devices are currently undergoing fabrication.

Fig: Proposed device architecture for an inverter, utilising electrons as the charge carrier. The “N” and “P” charge-accepting layers represent the equivalent CMOS transistors. With positive VG, the electrons are pulled from the reservoir into the upper channel, and with negative VG, the electrons are pushed into the lower channel. With zero bias, the charge remains within the reservoir and the channels are resistive (off). The barrier layers can consist of grown semiconductor or deposited dielectric.

Acknowledgments: Thanks to the Leverhulme Trust for a PhD studentship for Jonathan Hall and to nextnano for access to their software.

[papers] Biosensors for Agriculture, Environment and Food

---

J. Ajayan, P. Mohankumar, R. Mathew, L. R. Thoutam, B. K. Kaushik and D. Nirmal

"Organic Electrochemical Transistors (OECTs)

Advancements and Exciting Prospects for Future Biosensing Applications" 

in IEEE Transactions on Electron Devices, vol. 70, no. 7, pp. 3401-3412, July 2023

DOI: 10.1109/TED.2023.3271960

Abstract: Over the past few decades, the field of organic electronics has depicted proliferated growth, due to the advantageous characteristics of organic semiconductors, such as tunability through synthetic chemistry, simplicity in processing, cost-effectiveness, and low-voltage operation, to cite a few. Organic electrochemical transistors (OECTs) have recently emerged as a highly promising technology in the area of biosensing and flexible electronics. OECT-based biosensors are capable of sensing brain activities, tissues, monitoring cells, hormones, DNAs, and glucose. Sensitivity, selectivity, and detection limit are the key parameters adopted for measuring the performance of OECT-based biosensors. This article highlights the advancements and exciting prospects of OECTs for future biosensing applications, such as cell-based biosensing, chemical sensing, DNA/ribonucleic acid (RNA) sensing, glucose sensing, immune sensing, ion sensing, and pH sensing. OECT-based biosensors outperform other conventional biosensors because of their excellent biocompatibility, high transconductance, and mixed electronic–ionic conductivity. At present, OECTs are fabricated and characterized in millimeter and micrometer dimensions, and miniaturizing their dimensions to nanoscale is the key challenge for utilizing them in the field of nanobioelectronics, nanomedicine, and nanobiosensing. URL

---

Y. Wu et al., 

"A Dynamic Concentration-Dependent Analytical I,–V Model for LG-GFET Biosensor" 

in IEEE Transactions on Electron Devices, vol. 70, no. 6, pp. 3255-3262, June 2023, 

DOI: 10.1109/TED.2023.3268139.

Abstract: In the past few years, liquid-gated graphene field-effect transistors (LG-GFETs) have been widely used in biological detection due to their unique advantages. An accurate transistor model is the basis of biological detection circuit design, however, the reported GFET models are mainly focusing on solid-gated GFETs. Therefore, it is essential to conduct the research on LG-GFET model. In this article, an improved  IV  model of LG-GFET is presented based on Fregonese’s model. An improved electric double-layer capacitor model is proposed for LG-GFET. Then, the relationship among iron concentration, bias voltages, and current is studied comprehensively. Furthermore, the drain current response change with time is taken into account and the dynamic concentration-dependent model is established. To verify the accuracy of the proposed model, LG-GFET is simulated in TCAD software and fabricated to perform the measurement. The simulation results and measurement results are compared with the model results, respectively. These results show that the relative root-mean-square error (RMSE) to both simulation and measurement results is less than 5.7%. It is revealed that the proposed model can be applied to biological detection and achieve high accuracy.URL

---

Special Issue "Biosensors for Agriculture, Environment and Food"

Biosensors (ISSN 2079-6374) an Open Access Journal by MDPI

Editor-in-Chief Prof. Dr. Giovanna Marrazza 

Department of Chemistry “Ugo Schiff”, University of Florence, Italy

Food safety has become a hot issue concerned by governments, people and society. Biosensors have been playing a greater vital role in monitoring agro-products and their production process to ensure end-foods’ quality and safety, and they usually demonstrate a lot of benefits, such as being sensitive, rapid, portable, cheap and especially suitable for on-site testing. So, this topic will concern the development of biosensors and analytical methods, especially for chemicals, microorganisms, biotoxins in agriculture, environment and food samples. It is suggested that biosensors should be in line with the trend of five “S”, Sensitivity, Specificity (Selection), Speed, Simultaneously, Small (Smart), and that all detection methods should be validated using agriculture, environment or food samples. Interdisciplinary research and integrative application research related to biosensors are also encouraged, including review articles and research articles.

[mos-ak] [Final Program] 5th International MOS-AK/LAEDC Workshop, July 2, 2023, Puebla (MX)

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

5th International MOS-AK/LAEDC Workshop

July 3, 2023, Puebla (MX)

Final Workshop Program

Together with Profs Benjamin Iñiguez Nicolau, and Roberto S. Murphy Arteaga, local MOS-AK/LAEDC workshop coordinators, the LAEDC Organizers as well as all the Extended MOS-AK TPC Committee, would like to invite you to the 4th International MOS-AK/LAEDC Workshop which will be organized as the virtual/online event on July 3, 2022, between 8:00am - 12:00pm (local MX time) as an in-person event in Puebla (MX) providing an opportunity to meet with modeling engineers and researchers from Europe and Latin America.

The final program of the 5th International MOS-AK/LAEDC Workshop is available online:

https://www.mos-ak.org/puebla_2023/

Online Event Registration is open; any related enquiries can be sent to registration@mos-ak.org or laedc@ieee.org 

Important Dates: 

• Final Workshop Program: June 2023
  
• MOS-AK: July 2, 2023, Puebla (MX)
• 8:00am -  12:00pm (local MX time) MOS-AK Workshop

W.Grabinski for Extended MOS-AK Committee

WG210623

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/mos-ak/CALp-Rj-DstFXM-h9S78FZ_k5kKj9oJXYV%3Dz_vGRgPzz0XnqP%3DQ%40mail.gmail.com.

[book] Device Circuit Co-Design Issues in FETs

Device Circuit Co-Design Issues in FETs

Editors: Shubham Tayal, Billel Smaani, Shiromani Balmukund Rahi, Samir Labiod, Zeinab Ramezani

ISBN 9781032414256280 Pages 269 B/W Illustrations 

August 22, 2023 by CRC Press

Description

This book provides an overview of emerging semiconductor devices and their applications in electronic circuits, which form the foundation of electronic devices. Device Circuit Co-Design Issues in FETs provides readers with a better understanding of the ever-growing field of low-power electronic devices and their applications in the wireless, biosensing, and circuit domains. The book brings researchers and engineers from various disciplines of the VLSI domain together to tackle the emerging challenges in the field of engineering and applications of advanced low-power devices in an effort to improve the performance of these technologies. The chapters examine the challenges and scope of FinFET device circuits, 3D FETs, and advanced FET for circuit applications. The book also discusses low-power memory design, neuromorphic computing, and issues related to thermal reliability. The authors provide a good understanding of device physics and circuits, and discuss transistors based on the new channel/dielectric materials and device architectures to achieve low-power dissipation and ultra-high switching speeds to fulfill the requirements of the semiconductor industry. This book is intended for students, researchers, and professionals in the field of semiconductor devices and nanodevices, as well as those working on device-circuit co-design issues.

Table of Contents

1. Modeling for CMOS Circuit Design. 

2. Conventional CMOS Circuit Design. 

3. Compact modeling of junctionless Gate-All-Around MOSFET for circuit simulation. 

4. Novel Gate-Overlap Tunnel FETs for Superior Analog, Digital, and Ternary Logic Circuit Applications. 

5. Phase Transition Materials for Low Power Electronics. 

6. Impact of total ionizing dose effect on SOI-FinFET with spacer engineering. 

7. Scope and Challenges with Nanosheet FET based Circuit design. 

8. Scope with TFET based Circuit and System Design. 

9. An overview of FinFET based Capacitorless 1T-DRAM. 

10. Literature Review of the SRAM Circuits Design Challenges. 

11.Challenges and Future Scope of Gate-All-Around (GAA) Transistors: 

Physical Insights of Device-Circuit Interactions.