Jonathan Hall and Manus Hayne
Logic Without CMOS: A III-V Semiconductor, Single Charge Carrier Approach to Digital Logic
WOCSDICE-EXMATEC 2023, Palermo (Italy), 21-25 May 2023
Department of Physics, Lancaster University, Lancaster, United Kingdom
Abstract: A new patent-pending approach to digital logic devices is proposed as an alternative to complimentary metal-oxide-semiconductor (CMOS) logic. A novel III-V semiconductor digital logic device combines both the “n” and “p” equivalents of CMOS into a single heterostructure device using just one type of charge carrier. The device, which forms an inverter, consists of two charge-accepting channel layers which sandwich a central electron (or hole) reservoir. Under zero bias the charge remains in the reservoir with both channel layers absent of free charge carriers (off state). Once a bias is applied to the gate, charge is either pushed into the bottom channel (negative bias) or pulled into the top channel (positive bias) turning one channel on whilst the other remains off. Thus, the complementary behaviour of logic, in which one part of the logic element is on and the other is off, is achieved without the asymmetry of hole and electron mobility. Proof of concept devices have been designed in both the well documented GaAs/AlxGa1-xAs system and in the 6.1Å family of semiconductors. One-dimensional, room temperature energy-band simulations using nextnano++ (software for semiconductor devices) [1] have shown effective and symmetric logic function at low voltage and an excess of 1,000× charge density ratio between the two channels under operation. Proof of concept devices are currently undergoing fabrication.
Fig: Proposed device architecture for an inverter, utilising electrons as the charge carrier. The “N” and “P” charge-accepting layers represent the equivalent CMOS transistors. With positive VG, the electrons are pulled from the reservoir into the upper channel, and with negative VG, the electrons are pushed into the lower channel. With zero bias, the charge remains within the reservoir and the channels are resistive (off). The barrier layers can consist of grown semiconductor or deposited dielectric.
Acknowledgments: Thanks to the Leverhulme Trust for a PhD studentship for Jonathan Hall and to nextnano for access to their software.
