[review] SOI devices and their basic properties

Rudenko, T. E., A. N. Nazarov, and V. S. Lysenko

The advancement of silicon-on-insulator (SOI) devices and their basic properties

Semiconductor Physics, Quantum Electronics & Optoelectronics 23, no. 3 (2020)

DOI: 10.15407/spqeo23.03.227

* V. Lashkaryov Institute of Semiconductor Physics, NAS of Ukraine, 45, prospect Nauky, 03680 Kyiv, Ukraine

Abstract. Silicon-on-insulator (SOI) is the most promising present-day silicon technology. The use of SOI provides significant benefits over traditional bulk silicon technology in fabrication of many integrated circuits (ICs), and in particular, complementary metal-oxide-semiconductor (CMOS) ICs. It also allows extending the miniaturization of CMOS devices into the nanometer region. In this review paper, we briefly describe evolution of SOI technology and its main areas of application. The basic technological methods for fabrication of SOI wafers are presented. The principal advantages of SOI devices over bulk silicon devices are described. The types of SOI metal-oxide-semiconductor field-effect transistors (MOSFETs) and their basic electrical properties are considered. Keywords: silicon-on-insulator (SOI), metal-oxide-semiconductor field-effect transistor (MOSFET), multiple-gate transistor, ultra-thin-body SOI transistor, fully-depleted SOI transistor, interface coupling.

FIG: Equivalent capacitance circuit of the long-channel bulk / PD SOI MOSFET (a), and FD SOI MOSFET (b). Subthreshold characteristics of FD SOI MOSFET and bulk / PD SOI MOSFET (c).

[paper] Fast and Expandable ANN-Based Extraction

Jeong, HyunJoon, SangMin Woo, JinYoung Choi, HyungMin Cho, Yohan Kim,

Jeong-Taek Kong, and SoYoung Kim

Fast and Expandable ANN-Based Compact Model and Parameter Extraction for Emerging Transistors IEEE Journal of the Electron Devices Society (2023)

DOI 10.1109/JEDS.2023.3246477

Abstract: In this paper, we present a fast and expandable artificial neural network (ANN)-based compact model and parameter extraction flow to replace the existing complicated compact model implementation and model parameter extraction (MPE) method. In addition to nanosheet FETs (NSFETs), our published ANN based compact modeling framework is easily extended to negative capacitance NSFETs (NC-NSFETs), which are attracting attention as next-generation devices. Each device is designed using a technology computer-aided design (TCAD) simulator. Using device structure parameters, temperature, and channel doping depth as input variables, we construct a dataset of electrical properties used for machine learning (ML)-based modeling. The accuracy of predicting device electrical characteristics with the proposed ANN-based compact model is less than a 1% error compared to TCAD, and simulation results of digital and analog circuits using the proposed compact model show less than a 3% error. This allows the ANN-based modeling framework to achieve accurate DC, AC, and transient simulations without restrictions on device technology. In particular, temperature and process variables such as channel doping depth, which are not defined in the compact model parameters, are easily added to the previously presented five key parameters. Instead of conventional complex compact modeling and MPE work, we propose a method to create fast, accurate, flexible, and expandable ML-based Verilog-A SPICE models with design technology co-optimization (DTCO) capabilities.

Fig A: Conventional model parameter extraction flow

Fig B: The proposed ANN-based model parameter extraction flow

Acknowledgments: We thank the reviewers for improving the contents of the paper. This work was supported by an Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korean government (MSIT) (No.2021-0- 00754, Software Systems for AI Semiconductor Design) and by a National Research Foundation of Korea grant funded by the Korean government (MISP) (NRF-2020R1A2C1011831). The EDA tool was supported by the IC Design Education Center (IDEC), Korea

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[ElectronicsB2B ] #TSMC To Build Second #semi #Foundry In #Japan https://t.co/v8BTcb97vh https://t.co/rvvCz2MTgY

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[C4P] FSiC 2023

The 2023 Free Silicon Conference (FSiC)

will take place in Paris (Sorbonne)

on July 10-12, 2023 (Monday to Wednesday)

This event will build on top of the past FSiC2019 and FSiC2022 editions. The conference will connect experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will cover the full spectrum of the design process, from system architecture, to layout and verification. After the daily talks, the discussion will continue until late in an informal and relaxed atmosphere.

Participation to the conference is free of charge, but the attendance must be reserved per email at fsic2023 'at' f-si.org. Details will be announced on this page and over the mastodon channel. The slides and the video recordings of the talks will be published on our website.

Discussion topics of the 2023 Free Silicon Conference (FSiC) 

• High-level design
• Hardware security
• On-going FOSS silicon projects
• Memories
• Foundries and free PDKs
• Transistor Compact/SPICE/Verlog-A modeling
• Place-and-route tools
• Parasitic extraction
• Design rule checking
• Schematic editors
• Photonics
• Sustainability

Submission: For proposing a talk, please submit a title and a short summary at
fsic2023 'at' f-si.org.

FSiC Organizing Committee

Review of cryogenic neuromorphic hardware

Md Mazharul Islam¹, Shamiul Alam¹, Md Shafayat Hossain³, Kaushik Roy³, 

and Ahmedullah Aziz¹,

A review of cryogenic neuromorphic hardware

Journal of Applied Physics 133, no. 7 (2023): 070701

DOI: 10.1063/5.0133515

1Department of Electrical Engineering and Computer Science, University of Tennessee, Knoxville, Tennessee 37996, USA
2Department of Physics, Princeton University, Princeton, New Jersey 08544, USA
3Department of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47906, USA

ABSTRACT: The revolution in artificial intelligence (AI) brings up an enormous storage and data processing requirement. Large power consumption and hardware overhead have become the main challenges for building next-generation AI hardware. To mitigate this, neuromorphic computing has drawn immense attention due to its excellent capability for data processing with very low power consumption. While relentless research has been underway for years to minimize the power consumption in neuromorphic hardware, we are still a long way off from reaching the energy efficiency of the human brain. Furthermore, design complexity and process variation hinder the large-scale implementation of current neuromorphic platforms. Recently, the concept of implementing neuromorphic computing systems in cryogenic temperature has garnered intense interest thanks to their excellent speed and power metric. Several cryogenic devices can be engineered to work as neuromorphic primitives with ultra-low demand for power. Here, we comprehensively review the cryogenic neuromorphic hardware. We classify the existing cryogenic neuromorphic hardware into several hierarchical categories and sketch a comparative analysis based on key performance metrics. Our analysis concisely describes the operation of the associated circuit topology and outlines the advantages and challenges encountered by the state-of-the-art technology platforms. Finally, we provide insight to circumvent these challenges for the future progression of research.

FIG: (a) Biological neuron connected with multiple neurons through synapses. The inset shows the transportation of the neurotransmitter. (b) Electronic model of a neuromorphic system showing the integration of weighted spikes. (c) Several conventional hardware platforms. (d) Several cryogenic platforms for neuromorphic hardware. (e) Input spikes (Vin), corresponding membrane potential (Vmem), and output spike (Vout) of a leaky integrating and fire (LIF) neuron. An output spike is generated after Vmem crosses the threshold voltage (Vth). (f) Switching speed and switching energy comparison of conventional and cryogenic hardware.